New Math: 1+1=1?

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees.

Look across the entire SoC design chain, however, and the picture looks a lot different. Software is taking up an increasing amount of the NRE. The fact that more software engineers are being hired these days than hardware engineers is a well-known fact. What isn’t known among the hardware engineers is exactly what they do.

They don’t speak the same language. They generally aren’t even in the same age group as hardware engineers. And their verification techniques are completely different than on the hardware side. Perhaps even worse, inside many companies the budgets are split between the two sides rather than united into a single organization, giving each side unrealistic impressions about just how much it really costs to create a design.

While the upper management is fully versed in these kinds of cross-department costs, the lack of regular communication between the hardware and software teams has generated a lot of misinformation. They’re both part of the same process, and the aggregate cost is part of the same budget.

Perhaps even more baffling to both hardware and software groups is the cost of integrating third-party IP, which is becoming increasingly popular as chipmakers seek to cut their time to market. In many cases, that cost is split between both groups because it can have an effect on the performance of both the hardware and the software. Think memory and I/O IP, for example. Both hardware and software need to work with it effectively.

And finally, there are hardware bugs that can be fixed with software and software bugs that can affect the functioning of hardware. And when problems show up, particularly at the last minute, allocating costs may not be as clean as each side of the fence would hope—or as measurable.

The bottom line: The cost of developing chips at each new node is going up. You just have to look for those costs in different places than in the past.

–Ed Sperling