Two-Stage Hardware Fuzzer (TU Darmstadt)


A new technical paper titled "GoldenFuzz: Generative Golden Reference Hardware Fuzzing" was published by researchers at TU Darmstadt. Abstract "Modern hardware systems, driven by demands for high performance and application-specific functionality, have grown increasingly complex, introducing large surfaces for bugs and security-critical vulnerabilities. Fuzzing has emerged as a scalable sol... » read more

Generating And Evaluating HW Verification Assertions From Design Specifications Via Multi-LLMs


A technical paper titled “AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs” was published by researchers at Hong Kong University of Science and Technology. Abstract: "Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically describe... » read more

New Math: 1+1=1?


From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more