Three challenges stand out — scaling performance and capacity; ensuring silicon safety and reliability; and reducing development turnaround time.
Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5D/3D configurations, and memories embedded within system-on-
chip (SoC) devices.
Among the many challenges of memory design, three stand out: scaling performance and capacity; ensuring silicon safety and reliability; and reducing development turnaround time (TAT). This white paper discusses these challenges, describes the requirements for viable solutions, and introduces the Synopsys approach to addressing the challenges. It presents four major areas of innovation in memory development: design technology co-optimization, memory design shift left, digitization of memory design, and design for reliability.
Click here to read more.
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