Minimizing The Risk Of Electromagnetic Crosstalk Failures

Leading semiconductor markets, such automotive, machine learning, large scale computing and networking, are driving the need for high density chips that integrate high performance digital cores with sensitive analog/RF IP, while operating at the lowest power and fastest bandwidth possible. These trends are increasing the sensitivity to electromagnetic (EM) coupling, and requiring designers to worry about  how to detect, analyze and fix EM crosstalk related issues in their designs.

Electromagnetic crosstalk is unwanted interference from one or more signals (aggressors) affecting another signal (victim) through energy coupling via electric and magnetic field. EM crosstalk impacts chip performance in an unpredictable manner and can have negative effects on jitter. It can distort key signals, causing logic errors and a variety of inexplicable system level problems.

Isolating and mitigating EM coupling is a difficult challenge since inductive coupling can happen through large non-obvious loops formed by structures outside the immediate neighborhood of a victim signal. So to accurately analyze one must model and extract all design elements that can contribute including power/ground nets, silicon substrate, package layers, bond/bump pads, seal rings, metal fill and decoupling capacitance, etc.

In advanced technology designs (e.g., 7nm and below), there could be many aggressor/victim pairs which can potentially cause EM crosstalk induced failures. However, analyzing every pair can be very time consuming, if not impossible. Note also that this has to be repeated across the frequency range of interest, since EM coupling is frequency dependent.

Obviously, what is needed is a tool that can quickly scan a large design and quickly assess EM coupling risk between all potential aggressor and victim nets. Furthermore, visualization of identified victim/aggressor net pairs can help engineers focus their efforts on the most critical areas of the design. For example, generating a layout view, where the design layout is overlaid by color gradients showing the intensity of EM coupling, can help engineers isolate the parts of the design that need further investigation and possible modification. This can also serve as a final signoff check to indicate that EM coupling is within an accepted threshold. The figure below illustrates the idea using Snapshots generated by Pharos, Helic’s new EM risk analysis tool. Pharos is built on Helic’s production-proven high capacity, high performance EM extraction and analysis engine.

Sample EM coupling “Heat Maps” showing aggressors for a select victim net at 3 frequency points 10G, 20G and 30G. Snapshots generated by Pharos, Helic’s new EM risk analysis tool.

Performing risk analysis to identify and fix potential EM crosstalk-induced design failure not only helps engineers focus their efforts on areas of the design with high-risk aggressor/victim net pairs but also enables them to uncover potential design flaws that could go undetected until post-tapeout. Engineers can feel confident that critical issues are addressed, as well as improve their productivity. Therefore, this is a critical step in the design process and should be performed as early as possible and throughout the design flow.