MIPI DSI-2 With VESA DSC Drives Performance For Next-Generation Displays

The Mobile Industry Processor Interface (MIPI) Alliance was formed in 2003 to address the fragmentation in the essential video interface technologies for cameras and displays in phones. Over the years, the alliance has significantly expanded its scope to publish specifications covering physical layer, multimedia, chip-to-chip, control/data, and debug/trace and software. With its broader mission, “MIPI” became a name rather than an acronym for the MIPI Alliance.

The first iteration of the MIPI Display Serial Interface (MIPI DSI) specification debuted in 2006. The specification – which defines the interface between processors and displays – achieved widespread adoption. Now its successor, MIPI DSI-2 is the leading display interface used in smartphones, tablets and laptop/tablet hybrids. It is also increasingly used by the automotive industry for dashboard displays and in-car infotainment systems, as well as in wearables, IoT and AR/VR devices.

Initially published in January 2016, MIPI DSI-2 supports ultra-high definition (4K and 8K) resolution demanded by new and future mobile displays. It specifies the physical link between the chip and display in devices such as smartphones, tablets, AR/VR headsets and connected cars. In addition to MIPI D-PHY, DSI-2 supports the use of MIPI C-PHY as the physical layer.

MIPI DSI-2 v1.1 incorporates two Video Electronics Standards Association (VESA) video compression standards in its transport layer: VESA DSC and VESA VDC-M. This means designers can now select a codec that gives them tremendous flexibility in resolution, bandwidth and power requirements. VESA introduced the first DSC standard in 2014 and it quickly became the industry standard for data compression across the display interface. DSC was the first to offer a low latency, low complexity codec expressly designed for this purpose.

But what’s motivating the need for video compression? Mobile display requirements have advanced rapidly over the past few years, with high-end smartphones now delivering 120 frames per second (fps) to support gaming and 4K video. OLED adoption by major smartphone manufacturers has made 100 Mbit frame buffers quite common. In the highly competitive mobile phone market, where display resolution is a key selling feature, the demand for bandwidth has been insatiable. In the past decade, display bandwidth requirements have risen by a factor of over 20x while the bandwidth capabilities of display interfaces have increased by a factor of only four to five.

Deploying visually lossless compression closes the gap. Visually lossless compression is supported by Display Stream Compression (DSC) algorithms and encoders which are typically integrated into mobile application processors. On the receiving side, DSC decoders are also integrated into the Display Driver Integrated Circuits (DDIC) chips found in the display modules of mobile phones.

An example is implementing a 4K (WQUXGA, 2400×3840) link requiring bandwidth of 15.93 Gbps. With MIPI D-PHY v1.2 running at 2.5 Gbps/lane, you’ll need 8 lanes to reach the needed bandwidth. With 3x compression, that WQUXGA link can be implemented with a far more compact and practical 3 lane architecture. In addition to minimizing the number of MIPI D-PHY lanes, DSC reduces the memory buffer, thereby enabling smaller footprints, power savings and reduced cost. The VESA DSC algorithm offers compression as low as 8 bits per pixel (bpp) without any perceptible differences, along with extremely low latency performance.

Unfortunately, with the higher data rates, implementation complexity rises. Integrated solutions allow designers to take advantage of the increases in performance that meet the demands of next-generation display applications. MIPI Alliance members Mixel, Rambus, and Hardent have come together to offer an integrated MIPI DSI-2 VESA DSC IP subsystem solution for display applications requiring high bandwidth and excellent power efficiency.

The subsystem achieves excellent effective bandwidth utilizing one or two DSI-2 links with MIPI D-PHY or MIPI C-PHY physical interfaces with VESA DSC visually lossless compression. It sets a new benchmark for performance, ease of implementation, and time to market using proven, broadly adopted IP.

MIPI technology has been critical to enabling the dramatic growth of the mobile phone market. Incorporating VESA DSC visually lossless compression extends the reach of MIPI DSI-2 to advanced mobile phones and a growing range of products including AR/VR, IoT appliances and ADAS/autonomous vehicles. Mixel, Rambus, and Hardent give designers an easy-to-implement solution that meets the demanding requirements of these next-generation display applications.

Additional Resources:

• Website: MIPI DSI-2 and CSI-2 Controllers
• Product Brief: Mixel, Rambus, Hardent MIPI DSI-2 VESA DSC IP Subsystem
• White Paper: MIPI Drives Performance for Next-Generation Displays