Multi-Patterning: Game Changer or Y2K?

By Joe Davis, Mentor Graphics

Every new technology node brings new process challenges that translate into design challenges. For the last five years, design rules and processes have had to deal with an increasing impact from nearest-neighbor and environmental effects from lithography, stress, and temperature. Where once cells could be designed and placed independently, now a cell’s real performance, and even its ability to be “DRC-clean,” can’t be known until it is placed in the layout. The 28nm technology has increased the number of effects and rules that must be accounted for quite dramatically. A 28nm foundry deck has twice the number of checks as a 90nm deck, and those checks are more complex and longer-range than ever before.

20nm and beyond will employ ever more complex technology tricks to get the densities and performance that we require for competitive end products. One of those tricks that is getting a lot of press is double patterning, or, more generally, multi patterning (MP), where the layout is split into multiple masks that will be superimposed on the wafer to get the desired patterns. There are a lot of challenges that must be overcome in order to bring this technology into production on both the process and design sides and we, as an industry, are still working out all of the details. To use an old saying, we are “laying the tracks in front of the train”….as usual.

On the design side, designers are asking themselves how they are going to be able to implement layouts with MP? If I can’t know how the layout will be decomposed into masks, how am I supposed to make the layout “MP-clean”? How is my router going to do that? Can I meet all of these new constraints and still make a chip that is more competitive than the last technology? Or should I just stick with the last technology? Is this the end of Moore’s Law?

Let’s review the potential impacts of MP on design implementation.

1. Custom layout. Most of the layers that will use MP will be the very layers that the custom designer has to deal with in his world – poly, active, contacts, M1, M2. If the only way to know if the layout is MP-clean is to run the sign-off DRC deck, the designer is going to need a lot of DRC. Approximations to the sign-off deck aren’t going to work very well, because once you find out there is a difference, it will be too late.
2. Placement. Even if each cell is MP-clean, there can be cell-to-cell interactions that will cause the composite to have MP errors. Will we have to make every cell MP-compatible with every other cell, or will the placer now have to know which cells can be placed next to each other?
3. Routing. Routing the entire chip and then checking for MP violations is untenable, as designers will likely have too many errors to resolve efficiently.
4. Floorplanning – How do you plan a chip if you don’t know what sort of conflicts you will have in implementation?

It is a daunting list, and some might argue that the result will be a massive change in the design flow to accommodate these new effects. But wait a minute…haven’t we heard this song before? Not so long ago, you could hear the same melody, with the words “DFM” instead of “Double patterning.” As we pointed out in a previous blog, DFM hasn’t gone away, but has become invisibly integrated into the design flows so that you don’t see it…and therefore you don’t hear about it.

Let’s take a look at each of the challenges above.

Custom design. Since the designer can’t be expected to learn the MP decomposition algorithms, there has to be another way. One way that designers will react is to do what they have done for every preceding technology – make up their own rules-of-thumb that keep them out of trouble most of the time. One of the potential downsides of this approach is a less optimized, and therefore larger, layout. Of course, no one knows how much larger yet, or how well this will work.

The other alternative is to bring the sign-off checks into the layout creation process. Stream-out has been working for a very long time, but that methodology was predicated on the assumption that the errors could be fixed once, and that there would be few loops. If there are going to be many loops, each loop has to be shorter. OK…sign-off DRC is available today on the fly inside the design tool. With sign-off DRC available during design, the layout designer doesn’t have to learn MP—he gets MP feedback as he puts the layout together. No need for a new tool or a new paradigm, but simply letting two existing tools work together as they should.

Placement. Even if each cell is independently clean, they can interact to cause MP conflicts. The obvious approaches are to either make the cells interaction-free, or to enable the tool to make synthesis and placement choices based on a compatibility matrix between cells. The first approach is what most library providers have tried to do for lithography effects. But it turns out that you don’t have to make every cell compatible with every other cell, and most routers have at least some of the latter capability today. Of course, introducing more compatibility issues into the synthesis and placement may have an impact on run times, but library vendors and EDA vendors will work out a balance so that end users can get their designs out the door.

Routing. The router already has approximations of the DRC, lithography, and stress rules built into the tool so that it can achieve acceptable turnaround times and a DRC-clean layout. EDA companies are already building the same capabilities for double and multi-patterning into the routers so that they can produce MP-clean routes. In fact, the benefit of taking decomposition into account during routing has already been demonstrated and published. 1 If the built-in tools don’t provide sufficient accuracy for good results, the same trick that works for custom design works for routers— integrate the sign-off tool into the loop. To get the best results here, the router has to actually take advantage of the sign-off quality results.

In the end, MP is just the latest technical hurdle in a long history of similar challenges. While MP design may seem a daunting task at first, companies are already figuring out ways to make competitive products using MP technology, while EDA companies, foundries, and IP companies are figuring out how to enable them to do so more effectively and accurately. Looks like you can come out of your bomb shelter and resume breathing…
¹ Huang-yu Chen; Yao-wen Chang; , “Routing for manufacturability and reliability,” Circuits and Systems Magazine, IEEE , vol.9, no.3, pp.20-31, Third Quarter 2009
doi: 10.1109/MCAS.2009.933855
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5227779&isnumber=5227771

Joe Davis has worked on both sides of the EDA industry—designing ICs and developing tools for IC designers and manufacturers. He is currently the Product Manager for Calibre interactive and integration products at Mentor Graphics. Joe earned his BSEE, MSEE and Ph.D. in Electrical and Computer Engineering from North Carolina State University. When he is not applying his expertise in data visualization and engineering workflow, Joe enjoys sailing, gardening, hiking, and living and working in new places and cultures.