Author's Latest Posts


Designing And Testing FinFET-based IC Designs


By Carey Robertson and Steve Pateras The emergence of FinFET transistors has had a significant impact on the IC physical design and design-for-test flows. The introduction of FinFETs means that CMOS transistors must be modeled as three-dimensional (3D) devices during the IC design process, with all the complexity and uncertainty this entails. The BSIM Group of the UC Berkeley Device Group has ... » read more

A High-Level ‘How To’ Guide For Effective Chip-Package Thermal Co-Design


By John Parry and Byron Blackmore Concurrent design of a chip and its packaging environment is becoming more important than ever for several reasons. Designing a large, high power die, e.g. a System-on-Chip (SoC), without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight and performance perspective... » read more

A New World For Fill At N20


By Jeff Wilson and Jean-Marie Brunet There are many drastic changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has bec... » read more

Eco-Friendly Strategy


By Jeff Wilson If you want a winning fill solution at 20nm, you need a robust ecosystem in place with three main players. Each player has a specific role and, particularly as the new technology is defined, the players need to work in close partnership. Why is the ecosystem so important at 20nm? Because of the technological challenges, including process variability and design complexity. The... » read more

DFM is a Competitive Weapon


By Joe Davis, Mentor Graphics As my mom always told me, you always have a choice. The trick was, you had to be willing to accept the consequences of your decision. Don’t want to clean your room? Okay, but you can’t go out to play until you do. Easy enough to do the analysis on that one when you’re ten years old. But sometimes, understanding the consequences gets a little tougher, an... » read more

Multi-Patterning: Game Changer or Y2K?


By Joe Davis, Mentor Graphics Every new technology node brings new process challenges that translate into design challenges. For the last five years, design rules and processes have had to deal with an increasing impact from nearest-neighbor and environmental effects from lithography, stress, and temperature. Where once cells could be designed and placed independently, now a cell’s real pe... » read more

Support the Arts! in Custom Design Verification


By Joe Davis Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these ICs is also increasing, reflecting strong growth in wireless technologies such as WiFi, Bluetooth, 3G, and 4G, as well as GPS, audio, imaging, and sensor technologies. Market research indicates that while analog circuitry occupies only 20% of the ar... » read more

A Smart Filling Solution Yields Multiple Benefits


By Jeff Wilson, A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market. While there are numerous steps along the way, one task that must be performed is adding fill to the design. Fill is like design rule checking (DRC)—it’s not an optional step, because it is needed to ensure the manu... » read more

EDA’s Dr. Jekyll and Mr. Hyde


By Joe Davis The need for tool Integration and the reality of competition create a Jekyll and Hyde dichotomy for the EDA industry. Customers are demanding functionality that requires tight integration between tools even when they come from competing EDA companies. We have some examples of success, but this remains a challenging area. Customers can help or sit on the sidelines, but integratio... » read more