DFM is a Competitive Weapon

DFM is not something separate and apart from design rule checking (DRC).


By Joe Davis, Mentor Graphics

As my mom always told me, you always have a choice. The trick was, you had to be willing to accept the consequences of your decision. Don’t want to clean your room? Okay, but you can’t go out to play until you do. Easy enough to do the analysis on that one when you’re ten years old.

But sometimes, understanding the consequences gets a little tougher, and the pros/cons are a little less clear-cut. Like implementing design for manufacturing (DFM) techniques in your design and verification flows. If nobody’s making you do it, is the cost really justified by the outcome?

So, what is the cost of not adopting DFM? One thing I know—as the process nodes shrink, the cost rises. Why? Because at advanced nodes, you’re working with a process in which not all the effects are fully understood by anyone. That can lead to manufacturing surprises, and in our world, surprises are never a good thing.

For example, you send a DRC-clean GDS file to your foundry, and the next thing you know, it’s back. It failed OPC, or the filling requirements were not satisfied. Nothing you can do but go back into the design cycle to try and rectify the issues, which means more time ticking off the clock, and more money coming out of profits down the road. Or, your design goes through to silicon, and then fails in operation. Not only is that going to cost you real money, it’s also costing you goodwill and reputation, two assets whose value can be incalculable.

In any good design philosophy, we try to predict and understand the effects that happen within a process. DFM is one more tool in your arsenal. By deploying DFM techniques and technology throughout your layout guidelines, design reviews, and tapeout procedures, you can drastically increase your confidence that the designs you send to your foundry will pass their internal checks and perform as expected in production, while drastically reducing debugging and failure analysis all along the way. In turn, that lets you optimize your time to market and provides you a competitive edge in a competitive market.

DFM is not something separate and apart from design rule checking (DRC). DRC can be viewed as the minimum necessary to get a design successfully produced in silicon and working. DFM helps you improve the design, to make it more resistant to manufacturing vagaries, more likely to perform to expectations, and more likely to do so reliably throughout its life. DFM simply improves your control over your design process and its outcomes.

One example that comes to mind is a project we participated in with Cambridge Silicon Radio (CSR). By using process data from the foundry in conjunction with the Calibre suite of DFM tools, CSR was able to analyze both their processes and designs for optimization opportunities. They used critical area analysis (CAA) to identify changes to via redundancy and standard cell layouts that would improve the design’s resistance to manufacturing variation. They used chemical mechanical planarization (CMP) analysis and smart filling algorithms to resolve concerns with thickness variations. By starting at the intellectual property (IP) level, and employing these techniques all the way through to full chip, they were able to modify layout styles at an early stage, minimizing any rework later in the process, when it is more difficult and time-consuming.

CSR’s decision to implement DFM as a two-stage process was smart. They first sought to understand potential issues (using past designs as a starting point), and minimize them by developing guidelines prior to even beginning the designs. Next, once the designs were underway, they used DFM analysis tools to identify, prioritize, and fix any subsequent issues as quickly and efficiently as possible.

However, taping out “right first time” silicon is only half of the story. When you remember that revenue and market leadership are only generated after product ramp, you begin to appreciate how valuable reducing your time to production really can be.

At the recent TSMC OIP conference, Mark Redford, the vice-president of Advanced Technology at CSR, talked in even more detail about how DFM was key to their successful move from 130nm to 40nm. While higher functionality, which demands higher digital gate count and performance, was the driving factor in their move to the smaller nodes, CSR chips can contain 40-50% analog circuitry, and the preservation of that analog performance was critical to their market success. They used DFM technology to develop design guidelines and infrastructure ahead of the designers’ needs, and worked with the foundries to prime them for the types of designs CSR would be submitting, to ensure they hit volume ramping on time.

So, no, you don’t have to use a full complement of DFM technology. You can get by using only those techniques the foundries have deemed mandatory for some nodes and processes, such as lithography hotspot identification or dummy fill, as long as you’re willing to accept the consequences of that decision.

By using DFM to eliminate those manufacturing surprises and the subsequent respins, while also improving the reliability and performance of your product, you’re adding real value to your bottom line. Ask yourself, if you’re in a showdown at the IC corral with your biggest competitor, what do you want in your holster? One little DRC gun, or a full range of DRC and DFM weapons? I know what I’m packing…


Joe Davis has worked on both sides of the EDA industry—designing ICs and developing tools for IC designers and manufacturers. He is currently the Product Manager for Calibre interactive and integration products at Mentor Graphics. Joe earned his BSEE, MSEE and Ph.D. in Electrical and Computer Engineering from North Carolina State University. When he is not applying his expertise in data visualization and engineering workflow, Joe enjoys sailing, gardening, hiking, and living and working in new places and cultures.


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