Support the Arts! in Custom Design Verification

Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these ICs is also increasing, reflecting strong growth in wireless technologies such as WiFi, Bluetooth, 3G, and 4G, as well as GPS, audio, imaging, and sensor technologies.

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By Joe Davis

Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these ICs is also increasing, reflecting strong growth in wireless technologies such as WiFi, Bluetooth, 3G, and 4G, as well as GPS, audio, imaging, and sensor technologies. Market research indicates that while analog circuitry occupies only 20% of the area of modern mixed-signal devices, it can account for as much as 80% of yield loss. With that in mind, the smart companies are looking for ways to improve their analog/mixed-signal (AMS) design verification while maintaining or decreasing design cycle time.

AMS design has always been somewhat of an art, challenging designers to create layouts that satisfy all physical requirements while optimizing performance and minimizing area. When design rule checking (DRC) was relatively simple, AMS designers could effectively memorize all of the design rules, freeing them to focus on the qualitative factors of their designs. Now, with the significant increase in the number of drawn layers (it is not unusual to have 11 or more metal layers), an increase in the number of checks per layer, and a significant increase in the complexity of those checks (Figure 1), design groups working at 32 nm and beyond are reporting a significant increase in the difficulty of achieving a high-quality layout that is DRC-clean.

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Figure 1: The number and complexity of rules at advanced nodes has outstripped the ability of both the designers and built-in DRC checkers to keep up.

DRC is not even the only issue anymore. Just as with pure digital designs, the natural consequences of moving to smaller geometries means more design for manufacturing (DFM) issues resulting from manufacturing variability, and the need to close the design for timing, power and signal integrity across more design modes and process corners as multi-voltage domain designs are used to reduce power consumption. All this complexity greatly exceeds what can be handled manually or with current proprietary custom DRC checkers.

Traditional custom DRC checkers, which are nearly all incorporated into custom layout tools, assist the layout engineers while they are putting down polygons. However, none of these built-in DRC checkers cover the full spectrum of the signoff DRC and DFM checks, and none are qualified by the foundries for sign-off certification. As the gap between these built-in DRC checkers and the sign-off deck increases, layout engineers are spending more and more time iterating between signoff DRC checking and layout changes to get a clean design, meaning less time is spent creating new and optimized layouts.

Layout engineers simply want to do what they do best—design layouts. They don’t want the tools and the process to get in the way; they don’t want to spend endless hours waiting for batch runs to finish; they don’t want to fix one problem, only to find out the next day or even the next week that the fix creates another problem. The only answer that solves all of these issues is to find a way to bring signoff DRC/DFM verification right into the custom design creation process. Don’t bother with simple approximations—put signoff smack dab in the artist’s hands. By removing the separation between design and signoff verification—finding out right away if what they are doing is right or wrong, and being able to correct errors with confidence—designers can be more productive in the same amount of time. Why, it would be just like the “good old days,” when they could spend their time actually thinking about how to get the functionality that they need, rather than deconstructing and interpreting the complex details of today’s manufacturing restrictions. And that should make designers, their management, and their foundries, happy.

About the Author

Jow Davis

Joe Davis has worked on both sides of the EDA industry—designing ICs and developing tools for IC designers and manufacturers. He is currently the Product Manager for Calibre interactive and integration products at Mentor Graphics. Joe earned his BSEE, MSEE and Ph.D. in Electrical and Computer Engineering from North Carolina State University. When he is not applying his expertise in data visualization and engineering workflow, Joe enjoys sailing, gardening, hiking, and living and working in new places and cultures.