Multiple Dimensions Of Low-Power Verification With Portable Stimulus

There is little doubt that designing for low power is one of the biggest challenges for today’s system-on-chip (SoC) devices. The need to minimize power consumption is clear for the vast array of portable electronic devices that we use every day. Consumers expect most of their gadgets to last multiple days before they require recharging, and low-power design is the key to extending battery life. However, “green” laws and the desire to reduce power and air-conditioning costs mean that even “big iron” servers and network switches are being designed with low-power features.

One consequence of this trend is that verification of the low-power aspects of SoC designs has become complex and is consuming more of the project schedule. In last month’s post, we discussed one particular technique: using portable stimulus technology to automatically generate low-power tests based on the information contained in a standard Unified Power Format (UPF) file. In today’s post, we’ll explore some other aspects of low-power verification and discuss how portable stimulus can address them.

To start, UPF is by no means ubiquitous in SoC design and verification. Although UPF has been standardized as IEEE 1801-2015, it is based on several earlier power specification formats. Some of these are still in use today; verification engineers are too busy to re-write models that do the job unless they see a compelling advantage. There is also the issue of who writes the power specification file. It is hardware oriented, but control of low-power features in most chips is a combination of hardware and software. The software team is unlikely to develop or use a UPF file at all, and a hardware designer may not have the necessary system-level knowledge to develop a complete power specification.

Portable stimulus comes to the rescue. When a UPF file is available, a tool can build a portable stimulus model from which tests can be generated. If there is no UPF file, the design or verification engineers can write a model to define the power domains directly. Because the portable stimulus model is written at a high level of abstraction, it can capture the full system-level aspects of low power, including both hardware and software. Many key low-power features are under software control, so the portable test generation is software driven. These tests run on the SoC’s embedded processors and verify the design using many of the same real-world techniques as production software.

SoC designs may have hundreds of power domains and dozens of legal power states (allowed combinations of domains on and off). It can be quite complex to turn on and off power domains, exercising only legal power states, and coordinate power changes with other system activity. Shutting down subsystems in the right order to shut down the system, or waking them up again, can also be a challenging process. The combination of a powerful portable stimulus model and automatic generation of tests saves a great deal of time and effort in low-power verification.

Another virtue of portable stimulus is, of course, portability. From the same abstract model, tests can be generated for every verification platform and engine, tuned for the best performance. Targets include virtual platforms, simulation, in-circuit emulation (ICE), FPGA-based prototyping, and even silicon in the bring-up lab. Power-aware simulation, emulation, and prototypes model the low-power features so that they respond accurately to the software-driven tests. Only at the full-SoC level with realistic system test cases can the full range of low-power functionality be exercised and verified.

Portable stimulus is also valuable for estimating power consumption of designs. Although leakage current in advanced technologies is a much bigger factor in total power than in older geometries, the amount of switching activity across the design remains a key factor in calculations. Historically, the relatively short and simple tests run in simulation have not been representative enough of real-world software to yield accurate results. SoC teams have had to wait until they had an operating system and a real application or two running on ICE or prototypes.

A portable stimulus tool such as such as the Cadence Perspec System Verifier can automatically generate extremely complex multiprocessor tests of arbitrary length. These will stress-test SoC designs very well with software-driven use cases representative of how the devices will be run in the real world. Thus, the amount of switching activity is high and yields power consumption estimates much closer to the final numbers than traditional simulation tests. Further, since the generated tests run on “bare metal” without the huge overhead and boot time of an operating system, it may be feasible to measure power consumption in simulation as well as in the hardware platforms.

In summary, verification of low-power SoC designs is a challenging task that benefits from as much automation as possible. With or without a UPF specification file, portable stimulus provides an unrivaled solution with multiple dimensions of value to design and verification teams.