New Business Models Emerge

Every node now brings new challenges, and new disruptions to the way chips are designed and developed.


By Ed Sperling
Globalization, complexity and the rising cost of chip development are changing business models across the semiconductor design world in some expected as well as some unusual ways.

On a global basis, each new process node propels a new wave of disaggregation and disruption as the costs of design continue to skyrocket. What used to be under one roof is now shared by many. This trend is hardly new. It dates all the way back to the 1970s, when large integrated device manufacturers such as IBM, Fairchild and Intel began looking to third parties to develop their EDA tools instead of doing it themselves. That was followed by transferring the teams that developed the software tools, cutting out the in-house fabs used to build the chips and, more recently, in-house development of IP.

“We’re now seeing an aggregation trend in the IP space and an amplified disaggregation in the semiconductor space,” said Brani Buric, executive vice president at Virage Logic. “You’re going to see further disruptions because the future will be measured in time to system, not time to silicon.”

These kinds of disruptions already are beginning to surface. One of the more interesting models to emerge recently puts a new spin on software as a service, which has met with only marginal success in the EDA world. Rather than vendors renting applications to design engineers and architects, a corporate park in Suzhou (located just outside of Shanghai) buys the tools from EDA vendors and offers them to tenants.

Hoya Microelectronics, one of Japan’s top three design service providers along with Toppan and Dai Nippon, set up shop in the corporate park in Suzhou earlier this decade. The company, which like its top Japanese competitors began life as a maker of photomasks, also provides back-end services such as place and route and implementation to RTL interfaces.

The Suzhou location works particularly well for Hoya, however. For one thing, it moves design closer to the customer base in China. For another, the lower cost of labor allows the company to run successive shifts so designs are done 24 hours a day.

“The whole idea here is incubate and stimulate,” said Ajay Alwani, a sales representative for Hoya. “They have a pre-negotiated low-cost access to tools from all the major EDA companies.”

Interestingly, the Suzhou park is run by the Singapore government. Given the fact that the Singapore government has approved the sale of Chartered Semiconductor to a wholly owned subsidiary of the Abu Dhabi government, it may signal a different focus for the country’s electronics efforts.

Another interesting model comes from a company called Formalized Design, which is based in Colorado Springs, Colo. The company has been sending out e-mails to chip designers advertising senior engineers from India, China or the Far East who are based in Costa Rica. According to the e-mail, companies can hire engineers at hourly rates ranging from as low as $39 per hour for coders working on ZigBee and OFDM firmware up to $62 per hour for analog and mixed-signal circuit designs.

By moving them to Costa Rica, engineers are in the same time zone as many North American companies. They also can visit for a couple weeks every three to four months without an H1-B visa, which solves one of the knotty problems of offshore development where visas are difficult to obtain.

Formalized did not return calls for comment, but some executives contacted by System-Level Design say they are starting to see more of these types of arrangements and unusual offers for outsourced engineering skills.

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