No-Compromise Packetized Test Improves DFT Efforts

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these trade-offs has been to use hierarchical DFT methods in a divide-and-conquer approach. In hierarchical DFT efforts, all implementation, including pattern generation and verification, is done at the core level, which presents some challenges.

To test a group of cores concurrently using a traditional hierarchical pin-mux scan test approach, scan channel inputs and outputs are connected directly to a limited number of chip-level pins through a set of muxes. Which cores can be tested together is based on the mux network, which must be determined early in the design flow. Access configurations must be created when more cores and/or chip-level pins are available for testing. This impacts the DFT implementation effort, silicon area, pattern retargeting complexity and test time.

Tile-based layout adds further complexity and constraints to DFT architectures. Cores are designed to abut one another such that connections flow from one core to the next, virtually eliminating top-level routing. Any connectivity between cores must flow through cores that are between them.

These restrictions may be managed more effectively using a packetized test delivery mechanism to decouple core- and chip-level DFT requirements. The Tessent Streaming Scan Network (SSN) from Siemens EDA provides just such a delivery mechanism. Tessent SSN allows core-level compression configuration to be completely independent of chip IO limitations. Cores tested concurrently are enabled through IJTAG programming, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort.

With Tessent SSN, the compression and number of scan channels for a core are determined based on what results in the most compact pattern set for that core alone. Scan compression can be configured once and for all cores used in multiple designs. SSN automatically distributes the available network bandwidth among the active cores based on scan pattern volume for each core, eliminating whitespace in the test data (Figure 1).

Figure 1. Bandwidth tuning is enabled by throttling data to cores with less test data, reducing padding and test time/data.

The bars on the left represent scan pattern retargeting before SSN. The bars on the right represent scan pattern retargeting with SSN. Each bar is representative of a core; the length of each bar is representative of each core’s scan data, which is delivered to the core retargeting.  The blue is scan data, and the orange is white space (padding). There is a lot of orange because many cores have less scan data than the two long blue cores. During scan pattern retargeting, while blue cores are running, the orange cores need to run too, so they get lots of 0s (e.g., white space, padding) until the blue cores receive their scan data.

The picture on the right shows how SSN changes scan pattern retargeting. You see much less orange because SSN automatically transfers the network’s bandwidth from the cores requiring less bandwidth to the cores requiring lots of bandwidth, eliminating the white space/padding.

Rather than having to trade off DFT implementation effort and manufacturing test cost, SSN lets you achieve the most optimal test data time and volume for your system-on-chip (SoC) without expensive design iterations.

Figure 2. SSN enables an accurate bottom-up flow with multiple test cost reduction capabilities.

How does it work?
Many SoCs that achieve high throughput by parallelizing processing contain several cores replicated multiple times. In pin-mux scan architectures, the scan inputs may be broadcast to identical core instances. Still, the scan outputs are usually observed independently to ensure lossless mapping and observability for diagnosis.

Tessent SSN is a bus-based scan data distribution architecture. It provides a scalable method for concurrently testing any number of identical and non-identical cores. It allows testing identical core instances in near-constant test time, independent of the number of available chip-level pins. Input data, expected responses and compare/no-compare mask data are delivered and scanned within each packet, as illustrated in Figure 3.

Figure 3. Testing any number of identical core instances. A pass/fail “sticky” bit is observed on the IJTAG output. The optional accumulated per-shift status can be added to the packet and observed on the SSN outputs.

Each identical core instance uses the same packet data as it synchronously moves through the network. Each core performs its on-chip comparison. On-chip compare allows you to use the “same packet data” to multiple identical cores.  The sticky status bits are in each core and uniquely indicate which one fails rather than looking at the summary data that says something failed.

Figure 4. Tessent SSN is used in a six-core design.

Implementing Tessent SSN in your design
The table below summarizes the requirements and recommendations for implementing SSN in a design. For instance, IJTAG infrastructure is required to program the SSN circuitry. A standard (Tessent or third-party) on-chip clock controller is necessary to enable independent shift and capture.

Two things should be taken into consideration during the design planning phase. First, compression should be optimized at the core level to provide the best results for that core in isolation (e.g., the most compact pattern set). There is no need to consider chip-level resources or even the planned SSN bus width. Second, at the chip level, the SSN bus should be planned based on the number of pins available and the block diagram of the design. The SSN datapath should be planned to pass through all physical regions of the design. You can reuse the scan inputs and outputs used for non-SSN design as inputs and outputs for the parallel SSN data bus. In addition to the actual connectivity, you will also plan for muxes as needed for debug return paths and pipelines along the parallel SSN bus required for timing. What is not needed is any upfront planning of which regions of the design run in parallel or relative order.

A comprehensive set of SSN verification capabilities, including DRCs, dedicated testbenches and network integrity patterns, is available throughout the flow to ensure potential problems or mistakes are captured early, after SSN insertion is complete and before synthesis. Later in the flow, loopback patterns help validate the SSN network down to the individual cores without fully simulating the scan patterns.

The failure diagnosis flow is virtually identical to a hierarchical DFT flow. Failures captured on the tester are reverse-mapped to core-level failures. After the reverse mapping, layout-aware diagnosis is performed without limitations.

Post silicon access
Tessent SSN can also be used for some of your post-silicon needs. For example, SSN can create toggle activity in the design for high-temperature operating life (HTOL) reliability testing. Since the SSN bus can operate with a single-bit SSN bus, there is no need to create unique patterns or load board requirements.

In addition to addressing DFT implementation effort and test data volume, it is also important to facilitate debug, yield analysis and failure analysis (FA). SSN includes dedicated capabilities that ensure established FA techniques such as Electrical Fault Isolation (EFA) can be used together with SSN.

At the recent International Symposium for Testing and Failure Analysis (ISTFA 2024), Lesly Endrinal, Silicon Failure Analysis Engineering Lead at Google, presented findings on the use of SSN. The paper “Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies” introduced new features intended to facilitate failure analysis on designs tested using SSN. It presented three innovative DFT features and strategies to enable electrical fault isolation in the SSN architecture, an industry first. As DFT and test technologies become more complex and inaccessible, it becomes vital for EDA vendors and designers to be more aware of their impact on EFI. Being more proactive in designing hooks for FA can result in a more seamless yield bring-up and design debug.

Industry results
Many other industry leaders have stated the success of using Tessent SSN over the past years. At the International Test Conference (ITC) North America 2024, Vishal Agarwal, Sr. Director, H/W Engineering with NVIDIA, explained how SSN is being used in their challenging designs. Anurag Jindal, Head of the DFX group at Ericsson, presented productivity gains using Tessent products, including SSN. At the Siemens User2User North American conference, Mikey Shahar at Intel stated, “Intel significantly reduced test time per part by 10-25%, resulting in a savings of ~$50M.”

Darshan Kobla, Senior Director at Microsoft, leading Test Strategy across all product segments, recommended keeping DFT efforts simple and predictable when designs are complex in his talk at ITC NA 2023. This presentation included how using SSN and packetized test has been successful at Microsoft. At ITC NA 2022, Dan Trock, Principal Engineer at Amazon Web Services, presented findings on reducing design effort, test time and power with SSN in AWS custom silicon.  These presentations, and others, are available online at https://eda.sw.siemens.com/en-US/ic/tessent/events/best-of-itc/

Conclusion
Tessent SSN enables simultaneous testing of any number of cores with few chip-level pins. It reduces test time and test data volume. With SSN, DFT engineers have a true SoC DFT solution that may be used without compromises between implementation effort and manufacturing test cost. This proven, once-in-a-decade technology is seeing success across the industry. The solution also won the Siemens Innovator of the Year award for outstanding invention in 2002, not an easy feat in a company as large as Siemens. To learn more about Tessent SSN, please visit https://eda.sw.siemens.com/en-US/ic/tessent/test/streamingscan/