No Mess, No Stress

A clean and tidy working environment is often a productive environment. Imagine a desk with a lot of clutter. One may lose precious work minutes every time we go searching for a lost paper on a cluttered desk. The same is true if you are working on your designs.

During the course of a design project, spirited and fast thinking design engineers run several experiments. Some of them are more successful than the others. At the end of the day, design engineers and teams often end up with design cells that do not make it to the final body of work. Often these cells are called “unused cells.” Very often, a previously released library is a starting point for future projects. The unused cells make their way from project to project and assume a life of their own. They are often responsible for clutter in a library and can be a source of confusion.

Fig. 1: Housekeeping of design libraries.

Housekeeping of the design libraries is universally agreed upon as a good management practice. However it often is a time consuming and difficult task. Manual review of each cell in a library that may contain a few thousand cells is tedious and prone to errors. SOS Virtuoso provides design engineers a handy tool for doing exactly this task. The design management platform allows engineers to find cells in a library that are not referenced by any other cells and are not a part of the hierarchy. The design engineer can prune through a list of these cells — a much shorter list and delete the cells that are not unused or unwanted.

Fig. 2: Unused cell clutter.

In the above example, it appears that the PLL library has an extra vco_driver. This would normally be difficult to trace down. All design editor tools, including Cadence Virtuoso, allow you to trace the hierarchy from a top level cell. This would flag all the cells that are in the hierarchy for the pll_top cell. However, it does not give the user a capability to directly find cells in the library but not in the hierarchy. The design engineer can use SOS Virtuoso to identify all the cells that are not in the hierarchy for the PLL top cell. In the above example, it would return:

• tb_pll – A testbench cell is expected to be flagged as “not a part of hierarchy”. It should continue to be a part of the library in its current form.
• vco_drv – A vco driver cell that perhaps was created during the development of the library but later on dropped. A cell like the vco_drv is a prime candidate for cleanup.

An uncluttered design environment is as important as an uncluttered desk. While an organizational behavioral specialist can help you keep an uncluttered desk, SOS7 can help keep the design libraries compact and clean.