High-Speed SerDes At 7/5nm


Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

Cloud Characterization


Library characterization is a compute-intensive task that takes days to weeks to complete. Runtimes for library characterization are increasing due to larger library sizes, higher number of operating conditions to characterize, as well as the need for statistical variation modeling in libraries at 22/20nm and smaller process nodes. Cloud platforms offer a way to accelerate library characterizat... » read more

No Mess, No Stress


A clean and tidy working environment is often a productive environment. Imagine a desk with a lot of clutter. One may lose precious work minutes every time we go searching for a lost paper on a cluttered desk. The same is true if you are working on your designs. During the course of a design project, spirited and fast thinking design engineers run several experiments. Some of them are more s... » read more

Get To Know The Gate-Level Power Aware Simulation


The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation


INTRODUCTION Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distin... » read more

Design Virtualization And Its Impact On SoC Design


At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC. Using conventional design methodologies, it is very difficult to know if the correct options have been chosen. There is simply ... » read more