Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation

Understanding the Liberty syntax and other non-standard behavioral model libraries.


Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distinctive attribute between a special MV cell and a regular standard cell. The special MV cells include isolation (ISO), level-shifters (LS), enable level-shifter (ELS), always-on buffers (AOB), feed through buffers or repeaters (RPT), diode clamps, retention flops (RFF), power switches (PSW), multi- and single- rail macros. This article describes the standard requirements for libraries and processing mechanism in power aware dynamic simulator, like Questa Power Aware Simulator (Questa PA-SIM) from UPF-based PA verification perspective.

Libraries play a crucial role in the entire design verification and implementation flow (DVIF). Specifically for PA design verification and implementation, special design attributes are mandatory in an industry standard library format, known as the Liberty library description syntax. The Liberty syntax is usually available with (.lib) file extensions. In PA verification, special Liberty cell-level and pin-level attributes are required to characterize standard, MV and Macro cells and identify their corresponding supply or power-ground (PG) pin connectivity.

Generic and specific cell Liberty syntax file (.lib) examples are shown below for LS, as a representative MV cell. The specific cell example will be used to provide a simplified explanation of UPF-based PA verification.

Example 1: LS Cell Generic Liberty Syntax

Example 2: LS Cell Specific Liberty Sample


The generic and specific examples prevail several attributes; for instance, the

and output_voltage_range’ are known as special cell-level attributes that categorize this particular cell as an LS. Hence when these attributes are missing, the LS will be treated as just a regular standard cell. All the remaining attributes in these examples (such as are termed as pin-level attributes.

It is worth mentioning that some of these Liberty attributes are also implied in UPF as predefined attribute names. UPF supports the specification of attributes of objects in a design. Hence UPF allows such attributes to be used with HDL specifications in design code or with Liberty attribute specifications in a Liberty library. Table 1 shows a few of the Liberty attributes that are relevant to the UPF predefined attribute names.

Continuing with the LS examples, the ‘pg_pin’ and ‘pg_type‘ attribute together facilitate specification of power, ground, and bias pin connectivity of the cell, which in general will correspond to the primary power (VDD, VDDO), ground (VSS), and bias (VNW, VPW) supply of the power domain where this cell actually belongs, as specified in UPF. The ‘input_voltage_range’ and ‘output_voltage_range’ are the voltage ranges (from 0.8 to 1.2 volt) for all the input or output pins of the cell under all possible operating conditions. The ‘related_power/ground_pin’ and ‘related_bias_pin’ provide the related power, ground, and bias supply connectivity information for each input or output logical port or pin of the cell.

Related supply is augmented with ‘pg_pin’ attributes that indicate the functionality of the supply, whether it is primary power or primary ground. For single rail cells, when there is only a single set of power and ground supplies, all the inputs or outputs have only one set of related supplies. However for multi-rail cells, especially the MV and Macro cells, like the LS in this example (which is a MV cell), usually possesses different related supplies for the input and output. Figure 1 shows the diagram of LS cell explained above with related PG-pin information for all input and output pin. Here the related supplies for input pin (A) is (VDD/VSS) and for output pin (Y) is (VDDO/VSS).

Figure 1: Level-shifter with related PG-pin information.

The ‘std_cell_main_rail’ attribute defines the primary power pin (VDD) that will be considered as the main rail. This is a power supply connectivity parameter that is required when the cell is placed and routed at the post P&R level. The ‘power_down_function’ expression identifies the Boolean condition that consists of the combination of the different statuses of the power, ground, and bias pins, which signifies when the output pin of the cell will be turned off by these power, ground, and bias pins. The ‘power_down_function’ is defined in the library exclusively for verification purposes only. More precisely, the function is entirely for UPF-based dynamic simulation, where it facilitates the verification tool to comprehend the corruption behavior for the cell when the power domain (where the cell resides) is powered-off or switched to a shutoff condition.

The corruption semantics are imposed by the PA simulator imply on internal sequential elements, input and output signals, ports, and pins of the cell to change their regular known values to unknown values, in the event of power down or inadequate power supply to drive those logics correctly. So it actually defines a rule set that decides, how logic elements essentially behave in response to reduction and disconnection of power. Corruption typically refers to the situation where the value of logic elements or signals becomes unpredictable. Hence, corrupted logic is usually assigned to 1’bx or 1’b0 or hiz depending on logic types or user preferences.

The detail on power down functions are further discussed in succeeding sections for other library formats. Liberty libraries are mandatory for post-synthesis, gate-level PA static verification and in certain circumstances they are also required for PA dynamic simulation. From the examples and discussion above it is evident that both the cell-level and pin-level attributes are mandatory for any MV or Macro cell Liberty syntax. However, only pin-level attributes are applicable for standard cells used in PA verification, since no special attribute is required to distinguish a standard cell. UPF 2.1 and 3.0 LRM mention supporting the Liberty 2009.06 release syntax; however the latest release by the open Liberty organization is 2015.12.

Apart from the Liberty standard library syntax, there are other formats of non-standard behavioral model libraries, mostly modelled in HDL with (.v or .vhd) file extensions. The (.v or .vhd) models are specifically required for dynamic simulation-based verification and obviously available in two different formats, PA and non-PA simulation (.v or .vhd) model libraries. Hence these libraries may or may not include the supply power and ground pin information. Standard and MV cell models are usually written as Verilog HDL modules and use constructs such as Verilog built-in primitives or user-defined primitives (UDPs) to express the relatively simple behavior of a standard cell. They may also be written as VHDL design entities (entity and architecture pairs) using VITAL package, which provides Verilog-like primitive modeling capabilities.

Similarly, hard macro simulation model libraries can be written in either language, using more complex behavioral constructs such as Verilog initial blocks and always blocks, or VHDL processes and concurrent statements. However, PA-Simulation Model and Non-PA-Simulation Model libraries are not standardized like the Liberty standards. The following are the examples of LS cell behavioral simulation libraries, modelled in Verilog HDL.

Example 3: LS Cell Behavioral Non-PA-Simulation Model Library

Example 4: LS Cell Behavioral PA-Simulation Model Library

It is evident from these examples that Non-PA-Simulation Model libraries are just functional behavioral models without any power, ground, and bias, or PG-pin information of a cell. Whereas PA-Simulation Model libraries provide more accurate power information with detail and exact matching PG-pin with its counterpart of standard Liberty (.lib) library. The PA-Simulation Model library also contains the power-down function (conditional assignment statement in Example 4) similar to its (.lib) file.

As the naming of simulation model libraries suggests, their construct actually governs the fundamental aspects of PA simulation. Hence it’s worth noting that a UPF-based PA verification environment may have all of these three different types of libraries; namely PA-Simulation Model, Non-PA-Simulation Model, and Liberty for any particular cell on different purposes, times, and phases of the design verification and implementation flow. However it completely depends on the simulation tool and UPF methodologies how these libraries are consumed, individually or in combination, how they are interpreted, and how they are processed to produce targeted PA verification results.

The next sections highlight the use-models of the previously defined Non-PA and PA simulation libraries (Example 3 and Example 4); specifically how these libraries are combined with UPF and their corresponding counter part of the standard Liberty (.lib) library to furnish PG-pin information to the verification tool and accomplish PG-pin connectivity, and power-down corruption activity for accurate PA simulation based verifications.

As mentioned earlier, the Non-PA-Simulation Model libraries are just behavioral functional models without any representation of supply ports or affiliated power states, in contrast to the power down functionalities available in Liberty libraries or PA-Simulation Models. The verification tool, specifically a simulator, identifies a simulation model as non-PA only when the PG-pin declarations are not available within the model. The simulator usually resolves PG-pin connectivity and power-related simulation corruption semantics in either of the following ways.

First the tool searches for the corresponding Liberty (.lib) file for the cell and connects all the PG-pins from the Liberty library to the corresponding power domain where the cell actually resides, specified in the UPF. Since the corresponding Liberty library of the cell is available, the output corruption of the cell is also performed based on the power-down functionality from the Liberty library. The second procedure emerges only when the Liberty library for the cell is not available. Hence the tool implicitly connects the cell to the primary supply of the power domain where it resides. The power-related corruption for this case, applies to the output of the cell, based on the status of the power states of the primary supply of the power domain, usually expressed as – simstate and shown below.

Here, it is assumed that the Non-PA-Simulation Model is instantiated with the hierarchical elements that belong to the sub1_PD power domain. There are two power states INT_ON with -simstate NORMAL when the output of the cell will remain unaffected; however, during INT_OFF with -simstate CORRUPT, the output will be corrupted. The Non-PA-Simulation Models are well suited for modeling standard cells with a single rail and are traditionally used for post-synthesis, gate-level functional verification or logic simulation in a purely non-PA verification environment. However, they can be straightaway accommodated to the PA simulation verification environment at the post-synthesis gate-level by combining with UPF and the corresponding Liberty standard library.


On the contrary, a PA-Simulation Model library completely represents all the power, ground, bias, and related supply ports or PG-pins of a cell. As well it defines the power down functionalities. The PG-pins in PA-Simulation Models are primarily defined as input and output ports; however they may also be defined as internal registers, wires, or as supply_net_type, supply0 and supply1 type etc. Although the internal types of PG-pins are more common in an extended PA-Simulation Model library explained in the next section.

The PA-Simulation Model also includes the behavioral code that monitors the supply ports and appropriately corrupts its internal states and outputs, in response to events or values on the power supply and logic ports. However, explicit connection of an external testbench and UPF power supply to these PA model’s supply ports is mandatory through UPF connect_supply_net or connect_supply_set explicit commands. The explicit UPF connections disable the simstate-based corruption semantics, unlike non-PA models explained in the previous section. Hence Questa PA-SIM allows the PA-Simulation model library (.v) to take precedence and apply corruption semantics by itself. The simulator drives only the appropriate supply values to the PG-pin of the cell — when VDD is turned off (Example 4), the output Y will become 1’bx. Obviously a corresponding Liberty (.lib) library is unnecessary for PA verification with PA-Simulation model library. The PA-Simulation models are more suitable for modelling multi-rail macros and specifically they are created for PA simulation-based verification at the post place-and-route PG-netlist level, since PG-netlists contain PG-pin connectivity as well as logical functionality of a cell.

Questa PA-SIM also supports UPF predefined attribute-based automatic connections, if a supply port has the UPF_pg_type attribute associated with it — either by an HDL attribute specification or a UPF set_port_attributes command, based upon its pg_type. In this case, the appropriate value conversion table (VCT) will also be inserted based on the pg_type of the port.

Example 5: UPF Predefined Attributes Usage in HDL

In addition to Non-PA-Simulation Model and PA-Simulation Model libraries, there is a combined form of functional and power aware simulation model libraries, often termed as Integrated or Extended-PA-Simulation model library. The requirements of such extended libraries comes from the distinctive verification artifacts that makes them usable for both the non-PA regular functional (logic) verification and PA verification environment, while keeping both the functional and power features active internally in both environments. This is desirable because it is sometimes convenient to have simulation models specifically for hard Macros that can be used in both of these verification environments, without adding extra levels of hierarchy and without leaving power ports unconnected. Only extended power aware simulation models makes this possible.

The fundamental power-related construction of Extended-PA models differs from PA-Simulation models in power port declaration semantics. While PA-Simulation models declare ports on the interface of the model as input or output types, Extended-PA supply ports are defined as internal wires or registers as well as supply_net_type, supply0, and supply1 types within the HDL simulation models. The following example explains the construct of Extended-PA-Simulation model.

Example 6: A Macro Cell Behavioral Integrated or Extended-PA-Simulation Model Library

The integrated model defines only the power supplies (DVDD, VDD, DVSS, and VSS) despite of other PG-pins, including bias and related power and ground pins usually available in its counterpart in the Liberty (.lib) format. However, the supplies are defined as internal objects representing assigned default constant values that enable normal operational mode for non-PA simulation. During PA simulation with Questa PA-SIM, when UPF supply nets are connected to those internal objects through explicit connections via connect_supply_net or connect_supply_set commands or through automatic connections based on the UPF_pg_type attribute (similar to PA-Simulation models), the UPF supply net overrides the default constant values of the model, and the model then behaves as a PA-Simulation model.

More specifically from Example 6, the power (VDD) and ground (VSS) are defined as supply1 and supply0, which complies with the UPF LRM specification for designating power as 1’b1 and ground as 1’b0 logic resolution, when both are in the On state. During PA simulation, Questa PA-SIM provides the connectivity to the VDD and VSS of the model with the corresponding power domain primary and ground specified in the UPF. Hence such models are readily usable in RTL (considering power as 1’b1 and ground as 1’b0 as constant values) as well as in post-synthesis gate-level PA-Simulation with UPF, where the actual physical Macro cells are already inserted (considering VDD and VSS are connecting through the UPF supply net and then they can be driven from testbench).

Even the Extended-PA-Simulation models are also usable for post-layout PG-netlist level PA simulation with UPF. This is because the physical connections of power and ground of the Macro cell are already available in the netlist, and UPF provides the hooks to the internally defined power (VDD) and ground (VSS) through supply net connections similar to post-synthesis gate-level PA-Simulation. It is worth mentioning here that the PG-netlist PA dynamic simulation based verification does not require UPF, when a regular PA-Simulation model is available. Table 2 summarizes the library requirements for Questa PA-SIM.

It is distinctive at this point that Extended-PA-Simulation models have greater adaptability in different simulation environments and in different levels of design abstraction — from RTL to PG-netlist. However, depending on the verification targets and objectives, particularly for PA verification, all four types of libraries may become relevant and useful. Although the requirements of these libraries differ, depending on design abstraction levels, both the Liberty (.lib) and simulation-models (.v) may not be required simultaneously for a design in a PA simulation environment. Hence it is also important to know how Questa PA-SIM processes libraries and specifies the order of precedence when considering only a particular type or when multiple types of libraries are available in a simulation environment.

When both PA-Sim Model lib (.v) and Liberty (.lib) are available, Questa allows PA-Sim Model (.v) to take the precedence and corrupt internals or outputs of the cell based on its own power-down function. But when only Non-PA-Sim Model (.v) is available, Questa initiates a driver or UPF -simstate based corruption.

On the other hand, when only (.lib) is available and it gets the highest precedence, Questa PA-SIM deploys a new set of analytical approaches for the (.lib) to proceed for corruption. At first Questa PA-SIM searches for cell-level attributes to identify if the cell is a macro through the is_macro_cell:true attribute. If this attribute is absent or different, then obviously the cell is not a macro, hence Questa proceeds with driver-based corruption. But when the cell is a macro, then Questa corrupts the input ports with either of the following in the listed order of precedence, depending on their availability.

For the output ports of the same macro cell, Questa looks for the following attributes, also in the listed order of precedence and depending on their availability.

But in case, if power_down_function is absent, then the tool searches for following attributes in order.

Hence the tool internally generates the new power_down_function from (2a) and (2b) as follows:

Even Questa PA-SIM extends macro library processing flexibility further in case the related or bias PG-pin (2b) and (2c) attributes are missing. Hence Questa proceeds with corruption with the bias pins only from their corresponding pg_pin and pg_type attributes as shown below.

Essentially Questa PA-SIM addresses numerous, possible, complex combinations of Liberty, non-PA, PA, and Extended-PA simulation model libraries, with extended flexibility to afford accurate dynamic simulation even when the Liberty syntax and attributes are inadequate.

[1] Design Automation Committee of the IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group, “IEEE Standard for Design and Verification of Low-Power Integrated Circuits”, Revision of IEEE Std 1801-2009, 6 March 2013.
[2] Design Automation Standards Committee of the IEEE Computer Society, “IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems”, IEEE Std 1801-2013, 5 December 2015.
[3]. P. Khondkar. The Concepts and Fundamentals of Power Aware Verification, first edition, New York, Springer, communicated, 2017.