中文 English

High-Speed SerDes At 7/5nm

How to place macros inside a PHY in 7/5nm SoCs.

popularity

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip.



Leave a Reply


(Note: This name will be displayed publicly)