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Challenges With Chiplets And Packaging


Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Next-Gen Design Challenges


As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

High-Speed SerDes At 7/5nm


Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

GDDR6 Drilldown: Applications, Tradeoffs And Specs


Frank Ferro, senior director of product marketing for IP cores at Rambus, drills down on tradeoffs in choosing different DRAM versions, where GDDR6 fits into designs versus other types of DRAM, and how different memories are used in different vertical markets. » read more