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Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)

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A new technical paper titled “Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM” was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ).

Abstract
“Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Scouting or Majority have been proposed for the implementation of logic Computing-in-Memory based on active 1T-1R crossbar arrays. The operation reliability of these concepts critically depends on the accurate readout current distinction. In this paper, we perform experimental tests for several non-stateful logic gates based on transistor-coupled resistive devices (further denoted as 1T-1R) using HfOx as the insulating material. The focus of our investigation lies on the operation reliability and the influence of operation parameters. Based on our experimental findings, we conduct a thorough statistical analysis, assessing the reliability and outline the limitations of non-stateful 1T-1R logic functions for Computing-in-Memory.”

Find the technical paper here. November 2024.

L. Brackmann, T. Ziegler, D. J. Wouters and S. Menzel, “Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM,” in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2024.3486376.



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