OIF Eyes Expanded Electrical Link Definitions For 112 Gbps

Why it is essential to have a range of experts at various stages of a 112 Gbps SerDes design.


The insatiable demand for more bandwidth, lower latencies, and higher speeds is driven by a diverse range of applications and use cases. These include artificial intelligence /machine learning, sophisticated ADAS systems for semi-autonomous vehicles, 4K-8K video streaming, eSports, and AR/VR.

With global IP traffic now measured in zettabytes (ZB) per year, hyperscalers and service providers are moving from 100GbE to 400GbE and beyond to support increased aggregate bandwidth, as well as more bandwidth density per square foot in the data center. In addition, mobile networks are transitioning from 4G LTE to 5G infrastructure to support more users, higher data rates, and an increase in data streams per base station.

The above-mentioned trends are prompting data centers to upgrade the terabit routers and switches at the heart of the network. Indeed, upgrading to 112 Gbps represents the latest advancement in high-speed signaling technology, as new 28.6 terabit network equipment will require 112G SerDes (with 256 lanes) to achieve their target bandwidth. This is precisely why the Optical Internetworking Forum (OIF) is developing multiple electrical link definitions for 112 Gbps data rates and beyond. Such definitions will help provide signaling over a multitude of link types including die-to-die, chip-to-chip, chip-to-module, medium-reach chip-to-chip and long-reach chip-to-chip (also known as backplane).

These definitions include:

  • Common Electrical I/O – 112G XSR: IA specifications are being formulated for die-to-die (D2D) and die-to-OE (D2OE) electrical I/O interfaces. These can be used to support Nx112G I/O links with significantly reduced power, complexity, and enhanced throughput density.
  • Common Electrical I/O – 112G Very Short Reach: IA specifications are being developed for a chip-to-module (c2m) interface which can be used to support optical modules (e.g., 112G, 224G and 448G) with reduced power, complexity, and enhanced density.
  • Common Electrical I/O – 112G in MCM: An implementation agreement is in process for a low power, ultra-short reach (<= 10mm) electrical die-to-die interface @ 75-116 Gbps per pair of wires across a Multi-Chip Module (MCM) substrate (targeting wide-bus high bandwidth applications).
  • Common Electrical I/O – 112G LR: An implementation agreement is in the works for a Long Reach electrical backplane interface operating @ 75-116Gbps signaling over up to 1000 mm of twinax cable with two connectors, or over a shorter length of PCB backplane trace.
  • Common Electrical I/O – 112G MR: This implementation agreement is targeting a Medium Reach electrical interface operating @ 75-116Gbps signaling over up to 500 mm of PCB with a single connector.

As the OIF notes, it may become necessary for equipment designs and architectures to transition from current materials and structures to support next generation rates. This will help address insertion losses, as well as take advantage of newer and alternate materials and equipment designs. To be sure, with speeds hitting 112 Gbps, engineers continue to adapt to the various challenges of designing high speed SerDes by upgrading the package design, enabling them to more effectively address high frequencies and tight electrical performance requirements.

In addition, higher speeds have prompted engineers to increase their reliance on the detailed modeling and design of highly programmable circuits, debug interfaces, and utilities. From the perspective of a customer, design experience and the ability to execute in a timely manner are essential. It is therefore critical for 112 Gbps SerDes vendors to include a range of experts at various stages of the design, such as package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists.

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