Old Problem, New Solutions

By Ann Steffora Mutschler
Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events.

“These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Mentor Graphics. “We’ve had to wrestle with them for some time. Fifteen years ago when I was doing microprocessor design at 0.35-micron at DEC (Digital Equipment Corp.) we had an electrical migration budget and the reason for that requirement was that DEC—which put chips into VAXes and things that would do your financial statements—essentially had budgets that said our chips will last 10 years and expected 1%t of them to have failures due to EM.”

That type of requirement was never applied to the mobile market because devices aren’t expected to last that long, and fabless companies historically have not been particularly concerned about EM. Automotive companies have been a different story because cars are expected to last for a decade or more. That’s all changing as designs scale and chips get smaller and smaller, however.

“There was an inflection point some time ago when we switched from aluminum to copper—at about the 65nm/40nm process node,” Robertson said. “The characteristics of copper made them much more robust against electromigration, so we bought ourselves a couple of generations of time. At 28nm and 20nm, the wires are now thin enough that regardless of the chip, they are running at very high frequencies so electromigration is a concern for nearly any type of designer, not just for those who expect their chips to last 10-plus years. It’s a concern for those who expect them to last one to even five years. It really gets down to the scaling of the geometries and why it’s such a concern.

ESD and EM require analysis of power/ground nets at the full-chip level. Source: Mentor Graphics

Smaller nodes magnify electrical effects
When the design moves to advanced nodes, reliability becomes one of most important challenges. Reliable chip operation increasingly is affected by environmental conditions, such as electrostatic discharge (ESD), electromagnetic interference (EMI), and soft error rate from radiation (SER), and these things could even damage devices on a chip, according to Tianhao Zhang, senior product marketing manager at Cadence. “In the meantime, the multiple power domain application requires the appropriate signal protection to make a device work, which is more susceptible to ESD.”

Arvind Shanmugavel, director of applications engineering at Apache Design said in terms of electromigration, the single biggest driving factor for making things more complicated is process migration. “What we have noticed over time is the transistor drive strength has almost remained constant over the different technology nodes, meaning they can push out the same amount of current from 65 to 40 to 28 and even going down to 20nm, but the wire geometries have decreased over these generations. The wires have become thinner and they have decreased in overall geometry sizes and the EM limits for these wires have also decreased over these different technology nodes. The EM limit is essentially how much current can be pushed to a unit area of metal for a particular technology node. This depends on the metal properties and so on. We have noticed that those limits have also decreased with technology migration.”

ESD on the other hand, is an event-based failure. Technology migration as well as design styles have affected ESD design. In terms of technology migration, ESD needs to be designed within the operating window of device breakdown and normal operation. “As we move from one technology node to another, our device breakdown characteristics have drastically decreased, meaning that the drain-to-source breakdown, the gate-to-source breakdown voltages have drastically decreased but the operating voltage of ICs has not really changed that much,” he said.

Interestingly, Mentor’s Robertson said some fabless semiconductor companies aren’t necessarily so concerned with reliability of chips over a 5- to 10-year span and equate ESD failures to yield issues/the cost of doing business. ‘It’s a hard problem so we’re willing to lose a couple of percent due to this simply because it’s difficult to verify or difficult to protect against.’ However a greater and greater portion of your circuit is going to be susceptible to ESD failures. The oxides of your transistors are so small these days that it’s not just a human with a large piece of static electricity that’s a concern, it is potentially what we would consider rudimentary voltages in the past not dissipated correctly and blowing the oxides of a delicate 28nm or 20nm oxide. A larger portion of the chip could fail due to these events and so there’s been a push for new techniques.”

New techniques fall into a couple of camps, none of which are really new. “Since the beginning, we’ve always been able to simulate. We could always run circuit simulation for electromigration or ESD. The problem, however, is as these chips get bigger, this really requires a transistor-level simulation, and transistor-level simulators cannot accommodate today’s chips because of the size of the designs–multi millions, billions of transistors. In order to do this appropriately, you need a transistor-level simulator. Even the best Fast SPICE tools are not going to accommodate today’s designs. And static timing, while people are doing full chip static timing sign-off, with these ESD, electromigration issues many times you need to go down to the device level. At 20nm, you need to have even more stringent rules that identify what’s possible or not [with EM] and I think you have to be more sophisticated with your analysis. For ESD I don’t think it changes all that much because you’re trying to find out which are the sensitive devices and what they can tolerate, and then if there are protection devices that will accommodate the charge or currents that are possible. It’s essentially a math problem.”

Cadence’s Zhang said a new industry approach called design for reliability is emerging, which consists of adding more protection to minimize or even solve the impact of ESD and EM. However the verification this protection is extremely challenging. Right now most of design houses do the verification manually by experts, which has the significant risk of missing design flaws.

Cadence, Apache, Mentor Graphics, Synopsys and others provide tools here to help designers automatically verify their designs.

Looking ahead
Solving full-chip challenges for reliability are very interesting because, “when you put more components on the same die or when you put more dies in the same package, you’re affecting the reliability behavior of that system,” Apache’s Shanmugavel said. “With IC integration, for example, we have seen a lot more IPs being integrated on the same piece of silicon and that really effects the ESD design of the full chip. Because every IP has its own power delivery network and for each PDN, we need to have ESD protection devices protecting the power, the ground and the signal nodes associated with that particular domain. With the increasing number of IPs being used today comes an increasing number of voltage domains. Similarly with the increasing number of voltage islands for low-power design comes a higher complexity of verifying ESD protection for all these domains.”

ESD has to be verified not only on every domain but must also be checked cross-domain. This means that between every power domain and any other domain on the chip, there must be some kind of an ESD protection to make sure that there is a reliable discharge path of current during an ESD event. “This is no longer possible by visible checks. ESD is one of those art forms where people have visually looked at a layout and qualified that it’s ESD ok. But that’s no longer going to be possible—it has to be translated into a rule-based check and not just an art form,” he explained.

“The ESD limits have not really changed over time — it’s the same ESD standard that we’ve been using for the last 25 years but the geometry sizes have obviously gone down quite significantly, so pushing the same amount of ESD current through the geometries and the geometry sizes going down, there is a higher propensity to metal burnout. That is a huge aspect in terms of ESD verification that has to be available in your analysis platform,” Shanmugavel concluded.