How to reduce the time and effort required for debugging RDC results.
The cost and schedule impact of design issues caught late in the design cycle have made engineers focus on RDC analysis of RTL designs. RDC analysis is challenging in a sense that it involves careful consideration of design reset strategies. Fixing RDC bugs properly often requires changing the reset architecture which can be very costly at late stage in the design cycle. Additionally, a poorly architected reset strategy can lead to reset bugs escaping to silicon thereby leading to prejudicial wastage of thousands or even millions of dollars, design respins, and project schedule slippage.
Evaluating the results from RDC analysis can take a significant amount of time to both understand and recognize the specific fault highlighted in the identified paths. By reducing the number of paths to review through functional false path detection and stable path inference, the RDC analysis tool reduces the time spent on these reviews while allowing a more directed focus on the identified, real issues that should be addressed in the design.
Using case studies conducted in partnership with a large semiconductor company, this paper shares how to implement effective RDC analysis noise reduction strategies and how an automated RDC tool helps reduce the amount of time and effort required to analyze and debug RDC results. Specific issues are highlighted that must be addressed to improve RDC results and ensure the highest fidelity in identifying real design issues.
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