The Pain of UPF/CPF

If your power intent is wrong, then everything else that follows will be wrong.


Without entering into a debate on the merits of the UPF and CPF, there is a very real and valid concern that designers have today regarding these power intent formats.

According to Krishna Balachandran, director of product marketing for low-power verification products at Synopsys, design teams are questioning the validity/correctness of the resulting code.

Because they are learning these new power intent formats and not writing Verilog or VHDL that they are used to, there is concern that there could be bugs in the power intent.

“It’s garbage in, garbage out. If my power intent is wrong, the synthesis tool, the place and route tool are going to do something and I’m going to get something at the end but it may not be the right thing. That’s an area of concern,” he said.

This may still be an educational issue, it seems to me. The languages are new enough that they just are not understood well enough yet.

Balachandran said another area of concern currently is that design teams want their verification tools to be able to not only check that the cells are connected and inserted, but they also want the tool to check if the functionality, as it is implemented, is correct.

“If I have an isolation cell and I have an enabled signal for that cell that is coming out of that power management unit – either on-chip or off chip—in my library definition I’ve said that when the enabled signal is high I want that isolation cell to go on,” Balachandran said. “And when the enabled signal is low, I want the isolation cell to be off. That’s the intended functionality. The cell that was implemented was given, let’s say, by a library group within a large company, or from a foundry or from a library company. But the library itself may have some problems. And the cell, once inserted in the design, or in the insertion and connection, may not be correct. Therefore, the cell may not function as it was defined in the library, so this kind of check is becoming increasingly important.”

However, this is not as simple as it sounds, because the tool must be intelligent enough to trace the logic from the source to the destination and make sure that nothing was changed in the interim.

Are these items above issues for you today? If so, how are you and your design team dealing with them? Please comment below!

~Ann Steffora Mutschler


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