Pathfinding For Power And Heat

New capabilities are a big first step; the next challenge to integrate it into existing flows and standards.


By Ed Sperling
There are many ways to measure power and heat in an IC, and each one of them adds tremendous value to a design. But there are still holes, and those holes are just beginning to get filled.

Power and heat have emerged as two of the most persistent problems in advanced designs, and there is no single or simple way to tackle either of them. Nevertheless, there is at least progress on this front.

“Power is a side of complexity that has many, many dimensions,” said Aart de Geus, chairman and CEO of Synopsys. “We have multiple power domains and we now have states between on and off. How do you deal with that with ones and zeros?”

At the highest level, high-level synthesis can be used to provide generalizations about whether one processor versus another, or one piece of IP versus another will save power. The challenge there is to link those HLS models with other models to make them useful. This has been an ongoing challenge for startups such as Calypto and Forte Design Systems, as well as Synopsys and Cadence. (Mentor Graphics spun off its Catapult C platform to Calypto last year.)

At the lowest level, starting with RTL and even down to the gate, measurements are extremely accurate and useful. The problem is that once RTL code is written, it’s more difficult to change. Providing that kind of information early, and in context, has been a major challenge. Apache Design has created an RTL Power model, for example, as well as an RTL power flow and a chip-package-system model and flow to extract that information early enough to include it in the RTL.

The big missing piece, however, has been even earlier in the design process. What happens, for example, if a processor from one vendor is substituted for a processor from another vendor? Or what if signal traffic is routed one way in a design versus another? These are important tradeoffs at the architectural level, and there has been only scattered progress in this area. That’s partly because most of the complex thermal and power modeling for advanced is still being done with spreadsheets rather than with automation tools.

Docea Power jumped into the market this week with what should be an interesting first step. Its new AceThermalModeler software is aimed at architectural-level exploration and analysis for heat and power. The focus is on early system floorplanning or partitioning, system packaging, integration architectures and power management policies. It’s a certainty there will be other entrants into this space of the next year or two. All of the major EDA companies and their customers have been talking about the need for this kind of technology since designs reached 40nm.


Thermal Map. Source: Doea Power.

Thermal Map. Source: Doea Power.

But Docea CEO Ghislain Kaiser said the spreadsheets literally have run out of room at advanced nodes. They cannot handle any more data. What’s needed now is a way of raising the level of abstraction with accuracy, and he says there is an opportunity between the complex algorithmic approaches used for signoff and the packaging data sheets that are too far from reality. It remains to be seen just how quickly this market will ramp up as a result of that, because the next challenge will be to integrate this kind of information—all of it, from the high level to the pathfinding architectural models—into existing flows. That includes companies designing chips, as well as the ESL flows that are created by the Big Three EDA vendors, and the modeling standards groups such as OSCI, which developed TLM 2.0.

All of this will take time, of course. Standards groups move cautiously and large companies don’t make rapid changes to flows that work. Still, the need for more analysis that can be integrated throughout the design process is clearly needed.