How to speed up verification of PCIe designs.
In this case study, PLDA explains how verification engineers can use Mentor’s Questa Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines. The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe interfaces with multiple AXI interfaces. PLDA and Mentor have collaborated throughout the different PCIe generations, enabling advanced leadership on the latest technologies together.
To read more, click here.
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