Plumbing 101: Current Leakage And What to Do About It

By Brian Fuller

Rising demand for mobile products and the march of Moore’s Law have created conditions for a perfect storm that threatens to swamp electronics designs and the market growth those designs target.

The catalyst for that storm is leakage, which worsens the smaller devices become. Even in an “off” state, systems can leak like poorly insulated houses. But as the nation thinks about energy usage on a large—making homes and buildings more energy efficient—the electronics industry also grapples with the best energy-efficient design tools and techniques.

Leakage wasn’t a huge consideration until recent years, with electronics designs not only enabling mobile phone market growth but also bringing mobility and smaller form factors into a host other markets as well, including smart meters, medical devices, and the like. Most of those need to be miserly with power because they’re battery operated. And if they’re not, a greater sensitivity to the impact electronics has on the overall power grid and our national energy consumption is an important consideration.

“Leakage is a huge problem for the industry, and it’s worse as we scale,” says Ted Speers, head of product architecture and planning and fellow at FPGA vendor Actel Corp.

And designer concern is scaling just as quickly. “The (concern) has gone from a 10% problem to a 60% problem in the past four years,” said Steve Carlson a vice president in Cadence’s R&D organization. He is referring to customer-feedback studies that rate the importance of various design issues, such as power, leakage, performance and timing.

There are different types of leakage and scores of methods, tools and technologies to minimize it. We’ll narrow the focus for the purpose of this article to device leakage, and a few ways companies are trying minimize the power drain.

Dr. Leaky, I Presume

 Leakage happens in capacitors as a small amount of current inevitably drains away in an off mode to transistors or diodes. Imperfections in the dielectric material insulating capacitors—which can occur in manufacturing—can contribute to the problem, discharging the capacitor. While the leakage is generally in the micro-ampere range, over time it will drain a portable device’s battery, rendering it useless until it’s recharged.

Leakage increases exponentially the thinner the insulator becomes. Electrons can also leak across semiconductor junctions between heavily doped P-type and N-type semiconductors—the tunneling effect. And they also can leak between the source and drain, when the device should be off—the sub-threshold leakage problem.

To lower threshold voltages, designers squeeze oxides thinner and thinner, but the thinner the oxide, the higher the sub-threshold leakage. Often leakage can be more than half of total power consumption. Some experts have estimated that each process generation increases leakage current by a factor of 10.

Given these physical challenges, it’s a wonder advanced portable devices have any battery life at all. But they do. Battles are waged every day from the transistor level up through system-optimization, each contributing its part to the war on leakage.

Fighting the good fight

Every company has a solution or a methodology to tackle their particular part of the leakage problem, all honed within the context of design tradeoffs. Some approach the problem from an architectural standpoint, some from a materials standpoint, others from a design-optimization standpoint.

“Power is never by itself. It’s part of a larger context,” says Cadence’s Carlson. “There’s a strong interrelationship with performance. To be energy efficient, you have to understand where you are with performance. If you’re meeting performance with margin, you’re wasting energy.”

On the leakage front, he notes, there aren’t “that many” weapons used: Body biasing, and voltage thresholding, among them. Body biasing is one relatively affordable approach to tackling leakage—changing the bias voltage to shift the V_T level.

“You’re not using an ion implant; you’re shifting a voltage domain into another region. There is an area overhead, and it’s more complex to verify,” he said.

Another area of innovative is in the process itself—using different dielectric value metal gates in the process to control.

“You get a combination of different materials at different layers that can dramatically reduced leakage,” Carlson said. “That’s a big boon to design community.” But at the same time, “You can’t count on that because there are manufacturability issues.”

Research done by NEC has found that body biasing can reduce sub-threshold leakage by an order of magnitude and that certain high-k gate dielectric materials can cut standby power consumption by up to 80 percent.

The Material World

Materials play a key role in managing leakage at the device level. One of the emerging players (and choices) in the leakage battle is silicon-on-insulator (SOI), an alternative to bulk silicon. At 45nm and 32nm, features within the device are both very tiny and can be subject to manufacturing anomalies, at least when using bulk silicon.

“The definition of the poly line that defines the gate gets rough. You get points where it’s narrower than you intended,” says Horacio Mendez, a former design engineer with Freescale and Motorola, who now heads the 26-member SOI Consortium, in Austin, Texas.

Using bulk silicon, while less costly as a material than SOI, can force designers to implant their transistors at the channel and under the gate to control leakage, and that adds cost to the design.

But SOI has a different charging mechanism than bulk silicon and therefore has better properties to manage leakage, Mendez said.

“At 180 and 130nm, SOI was used for high-frequency applications. IBM used it for servers,” Mendez said. “Then as technology shrunk more, people wanted to trade that frequency for lowering power, because power was becoming more of a problem than frequency. So you have less leakage, and that allows you to get higher drive current.” And higher drive current allows a designer to reduce power.

A Look from the Architectural Level

As SOI tries to become a more attractive and cost-effective option for a broad range of companies (Mendez sees price-parity with bulk at the 22nm node), other companies are addressing device leakage at the architecture level.

Actel has positioned itself in recent years as a low-power provider by marketing the flash-based nature of its programmable-logic devices. The FPGA market is generally divided into SRAM-based architectures and flash-based architectures. With the former approach, SRAMs are laden with transistors and therefore more prone to the leakage issues earlier discussed, such quantum tunneling and sub-threshold leakage.

The benefit of the SRAM architecture is it’s a less expensive process than the flash-based architectures, and the end device can be faster. If a vendor is targeting a market that’s not sensitive to power, say an industrial application that is always on, that approach might be beneficial.

FPGAs that contain a nonvolatile FPGA array can have significantly lower static power than SRAM-based solutions, making them an attractive alternative for power-sensitive applications. In fact, in some modes, such FPGAs consume as little as 5 μW. 

“The real pressure is coming from the Qualcomms and people making processors and stuff for cell phones,” Actel’s Speers says. “My impression with talking with major cell phones guys is that power is secondary after cost. But there are guys really thinking about the phone and trying to manage every microwatt in a cell phone.”

So the battle is being waged on all fronts by everyone in the semiconductor design chain, from device physicists to architects to materials and equipment vendors to system designers. Ultimately, optimization at the system level can deliver the biggest power improvement bang for the buck, but it all starts at the bottom.

“If we said we’re going to make hardware-software tradeoffs to come up with an optimal energy profile for a device, you can’t do it without the bottom up data,” Cadence’s Carlson says. “In terms of baseline analysis capabilities and techniques, on a scale of one to 10, we’re a six or a seven. The infrastructure is there”