The Power Of Analog

The shift into stacked die, expected to begin late next year with a big ramp in 2013, will shine a spotlight on analog design and its effect on power. For years, analog engineers have bragged about just how efficient their portion of a chip was versus digital.

We’re about to find out if they’re right. Stacking die will, to a much greater extent, decouple analog from digital and leave it open for examination. That may help to explain at least part of the motivation behind Synopsys’ proposed purchase of Magma Design Automation this week. Analog engineers, who have spurned automation flows in favor of point tools, will now have to play in the same sandbox as engineers working on other chips—and on the same time-to-market schedule.

They also will have to be part of the overall team that tackles power budget issues, which means trimming wherever possible. This isn’t so easy in analog, because maintaining high signal-to-noise ratio is more difficult in noisy environments. Moreover, in stacked configurations they won’t always know what chips will go where and what kinds of physical effects those other chips will have on their analog functionality. More analysis in this area will help, but with die thinned to as little as 50 microns and connected by TSVs, which can reverberate noise, this will be a major challenge.

Tools will help—particularly system-level tools that can analyze all pieces of the design early in the process. What-if tradeoffs will be necessary at the architectural level, and analog will be a key component in those decisions. Turning on and off analog die and/or blocks also is different than digital blocks. And process variations will affect each of them differently.

But no matter how different these worlds, they are now about to become part of the same team—along with software engineers, who often don’t even attach the same meanings to words. In many ways, stacked die will become a melting pot of talent—and they will expose rather vividly where the flaws are.