Power Is Now No. 1 Concern

One of the messages that came through loud and clear during DesignCon this week was the concern about power. In every design at advanced nodes, and even in some at older nodes, power has emerged as the top concern.

Current leakage is now considered a fact of life at 28nm. It can be managed, but never completely eliminated. And it occurs in both dynamic and standby power, in all modes, and in all structures. Certain substrates and insulation models help, but no solution is complete.

At advanced nodes, the issues involved in verifying power in advanced designs are becoming more complex, as well. Third-party IP needs to be fully characterized for power. Embedded software and firmware need to be accurately modeled across all modes of operation. Even application software needs to be accounted for, because parallelized software has different demands on a multicore system than software that can take advantage of only one or two cores. The more cores in use, the greater the heat generated.

There are some interesting technologies being developed to get heat out of SoCs. One involves chimneys, which is probably the least expensive solution. The problem is where the heat goes after it is released. The second involves mechanical movement of liquid through the chip, which functions much like an automobile radiator. But modeling these cooling systems has its own challenges, because all of this is relatively untested technology.

In 3D stacking, and to a lesser extent in 2.5D stacks using a high-speed connector, all of these issues become compounded. The market is split among who is actually working on 3D technology. Communications chip vendors such as Qualcomm have pushed very heavily into this arena, while rivals such as Broadcom have not. But almost all see it as an inevitable direction because of the difficulty of developing analog IP at advanced nodes, and once that happens they say power will be the key issue—again.