Power Panel: IP And Other Key Issues For Future Development

Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed.

Bhanu Kapoor: There are two components of power—dynamic and leakage. Dynamic is what gets used for some useful activity on a chip. Leakage is wasted power. To put this in perspective, at the 65nm technology node leakage power is about the same as dynamic power.

Dynamic power depends on the frequency, capacitance and supply voltage. Changing supply voltage makes a big difference.

Leakage has two components—sub-threshold and gate tunneling. The gate tunneling is addressed by high k/metal gate technology. The sub-threshold remains there and is growing exponentially. While it was not a factor at 130nm it has become a critical factor at 65nm and beyond. When you manage power, you have to manage dynamic power and leakage in active and standby mode.

You’ll need high voltage if you want to operate at high frequency. As such, you can reduce voltage if your application doesn’t need high performance. There’s a cubic effect on power consumption because of scaling voltage and frequency. In standby mode you want to completely switch off the supply. Power is a product of current and voltage. If you turn off the voltage you can eliminate most of the standby leakage.

There are various power management techniques to deal with leakage. (see fig. 1). Voltage is a key parameter to address power. It’s the use of voltage—and your design description language not allowing voltage to be an input—that have made design so difficult.

Fig. 1

You can’t be far away from what’s happening with process technology if you’re targeting your IP for future generations of chips. The process variation is a problem. You could be doing everything right, but process variations may lead to a leaky part. Unless you have controls such as adaptive body biasing to address leakage in those variations it’s going to be a potentially fatal factor.

There are different EDA tool flows and because of that we’ve got different formats for describing power. On top of that, soft IP is unqualified.

IP will be running in different power states, and there are different voltage levels for different portions of the chip. This information needs to be provided to SoC teams. Isolation and level shifting have to be taken into account. State retention is another technique. Bring-up current may be an issue. The spike in current could lead to voltage issues. For all of these reasons, if you’re a small IP vendor doing low-power design, life is very, very difficult.

Kesava Talupuru: There are a number of techniques you can use to reduce power.
With power gating you can shut off any of the pieces that are not in use to save on leakage power. With tree-root clock gating you can save dynamic power. With multi-voltage designs, for any part that does not require maximum frequency you can minimize dynamic power. And for multi-threshold libraries you can minimize the leakage power.

So what are the challenges for low-power verification? One is that traditional functional simulators are not power-aware. They assume that voltage is constant at zero or one. They cannot emulate protection gate behavior. They cannot model power ports and switches, and they cannot find structural errors. On top of that, the power-on and the power-down sequence checks are not adequate. They do not understand voltage transitions. When you do a reset they initialize the signal immediately, and when you power down the flops still retain value.

The verification environment should be power-aware. You need voltage-level aware simulation for dynamic voltage low-vdd standby techniques and you should simulate real silicon behavior. You should be able to model power switches and protection gates and check illegal power state transitions. And they also should support recovery sequences.

At MIPS we used three different techniques to deal with this. One is formal verification for the power manager unit, which gives you full control of logic, enables a small design size and provides formal proofs. A second is power-aware simulation for the entire system. This is useful for finding polarity isolation issues, retention and restore behavioral issues, and problems with power-up/power-down sequences. The static verification was basically lint checking. The tools can find any missing isolation cells or level shifters.

For the power manager we added hardware and software control. The software-related properties include read, write, hold and reset values. The hardware FSM properties included state transitions, illegal states, power up and power down sequences and hardware/software priorities.

We found a number of bugs using our flow (see fig. 2). Through formal, we found bugs in state transitions, illegal states and power up/power down sequence errors. We found errors in the power down where it needed to wait until all the transactions were completed. There also was a problem with the coherent to non-coherent switching. Using power-aware simulation we found missing isolation, some wrong isolation polarity and architectural bugs.

Fig. 2

FIG 2: KT-FINAL-DESIGNCON SLIDE 10