Prototyping ARM Cortex-A Processors Using FPGA Platforms

How to adapt ARM processor IP for FPGAs, and how to deal with partitioning across multiple FPGAs.


With the increasing cost and complexity involved in new SoC (System-on-Chip) designs, FPGA (Field Programmable Gate Array) prototyping is becoming an increasingly important, or even crucial, part of new SoC projects. By offering a way to get to hardware sooner, FPGA prototyping allows hardware verification and software work to begin earlier, before first silicon, effectively pipelining the design process. Modern reprogrammable FPGAs are flexible and versatile computing and prototyping platforms – the ease of reconfiguring the development system for testing successive passes at the overall design offers a major advantage to the developer and gives confidence in the design before committing to producing a costly ASIC. Prototyping in FPGA also allows for debug and observability techniques that would otherwise not be available, such as inserting signal probes directly in the FPGA fabric. However, prototyping an SoC by implementing it into an FPGA does present some unique challenges that need to be considered. The underlying FPGA architecture and resources offer both limitations and possibilities when mapping an SoC design onto FPGA.

In FPGA, it is rarely possible to achieve the speeds that the IPs being implemented are intended to achieve in silicon. Due to various factors (such as pin multiplexing), the maximum frequency in a multi-FPGA design has traditionally been constrained to speeds well below the fabric limit of the FPGA.

In the past, with smaller ARM cores and less complex systems, it was normally possible to fit an entire system onto a single FPGA. Currently, even given the greatly increased capacity and diverse set of resources available on modern FPGA platforms, with the current demand for more powerful application processors and larger ASSPs, all of the building blocks constituting a system might not always fit into a single FPGA – even if using the largest FPGAs commercially available at the time of writing. It is therefore sometimes necessary to break up the design into smaller blocks and fit them into several connected FPGAs. This presents the additional problem of how to best partition a system or design across multiple FPGAs.

In this whitepaper, we discuss commonly encountered issues when prototyping ARM Cortex-A class processors using FPGA platforms. We show how to adapt ARM processor IP for implementation in FPGA, and give guidelines on how to approach partitioning a system across multiple FPGAs. FPGA platforms, boards and tools vary between vendors and versions. For documentation and support on these, it is advisable to contact the relevant vendor directly. To read more, click here.