Reduce design iterations and improve product quality by moving critical checks earlier in the design cycle.
To keep up with the growing complexities of IC design, major semiconductor companies are adopting shift-left strategies. For verification, this means pulling much of the work into the physical design stage. By moving critical checks earlier in the design cycle, you can identify and resolve issues before they escalate, streamlining the overall development process.
The Calibre tools have been driving purposefully in that direction, transforming the way IC design teams approach physical verification. As part of the shift-left platform, Calibre Pattern Matching uses pattern-based productivity improvement features to help you easily verify that the layout design matches the intent, debug issues quickly and accelerate towards a clean tape out.
Many existing verification approaches rely on manual measurements and custom design rule checks (DRCs) that are time consuming to implement, data dependent, take time to react to requirement changes or are conducted late in the design cycle. This means that design teams might only catch critical symmetry and placement issues after investing a large amount of time and resources in the design, leading to costly revisions.
As an example, today’s ICs integrate a lot of IP, sometimes tens to hundreds of IP blocks sourced from custom development and third-party vendors. While the IP providers deliver a clean layout, it’s ultimately up to you, the IP customer, to confirm that each IP placement is accurate and free of errors. On top of that, you must also make sure the IP cells are not changed so they perform as spec’d and conform to IP guidelines. Figure 1 shows a layout with an IP row mismatch.
Fig. 1: IP row mismatch error in a memory cell array. The middle ram block is missing matches along one word line (towards the left) where a modification resulted in a change to the bit cells.
As for symmetry checking, it’s crucial in designs such as AMS, silicon photonics, MEMS etc., but it is also time consuming and often requires custom rule checks. During device-level layout, a comprehensive set of symmetry rules are often not available. Designers utilize their best symmetry practices, but comprehensive symmetry verification must be put off until custom rules are available. Manual symmetry checking methods, such as using measurement tools, are not only time-consuming but also prone to human error. Even correct-by-construction techniques such as cell mirroring or cloning can lead to a false sense of accuracy if not properly validated through an alternate method. This can lead to symmetry violations persisting in the layout much longer than necessary.
This is where a shift-left verification strategy, enabled by recent pattern matching capabilities, enters the story. By moving critical checks earlier in the design cycle, you can find and fix issues before they escalate, streamlining the overall development process.
The key to this shift-left approach lies in the power of pattern matching technology. You can now leverage pattern-based solutions for accurate checks of symmetry, IP placement accuracy and other crucial design attributes as you work on the layout.
Verifying an intended symmetrical device does in fact have symmetry for every layer and polygon is “click-button” easy. It can be done early, during device construction, and often, repeatedly as the device layers are built up and between every edit/fix. Imagine having the symmetry guarantee for a layout block as it is placed within the context of a larger chip. Now once placed, the context surrounding that block can also be checked for symmetry to guarantee that neighboring circuitry influences each side of the layout block equally. To verify a placement and/or context, the designer needs only to reselect the checking region within the design environment while paired with Calibre RealTime. Figure 2 shows a screen shot of interactive symmetry check in a design layout environment.
Fig. 2: Screenshot of Calibre interactive symmetry checking demonstrating how symmetry checking is conducted within the Cadence design environment using Calibre RealTime.
If your design includes many integrated custom and third-party IP blocks, verifying the placement and integrity of these critical components is paramount. Pattern matching solutions let you proactively check IP placements, ensuring that each block is correctly positioned and free from errors. By catching IP-related issues early, design teams can mitigate the risk of late-stage functional problems and enhance the overall quality of the final product.
For IP checking, Calibre Pattern Matching automates the verification of the presence, placement and integrity of each IP instance in the layout, starting with a layout containing reference IPs and dynamically adjusts based on user selections and no rule coding.
When verification jobs complete, the work to understand and debug results is just beginning. To prioritize and categorize errors more effectively, you can use the highly automated Calibre RDB Classifier to organize and manage verification data. As verification progresses, the RDB Classifier gives detailed insights into results, making it easier to understand error severity and focus on the most critical problems first. Streamlining the debug process improves designer productivity; instead of sifting through large volumes of DRC violations, you can quickly identify and address the root-cause issues, prioritizing the most critical problems. This organized, actionable feedback helps you make informed decisions and accelerate the path to tape-out. Figure 3 illustrates the RDB Classifier capabilities.
Fig. 3: The results databases (RDB) hold a wealth of information for current and future design improvements. The Calibre RDB Classifier’s class IDs and duplication counts bring attention to results with the highest context repetition within the rule check.
Early verification of symmetry and IP placement with pattern matching technology has a profound impact on IC design productivity and time-to-market. By addressing critical layout issues early in the design cycle, teams can significantly reduce the number of design iterations required, accelerating their path to tape-out.
Moreover, the real-time feedback and streamlined debugging process with Calibre Pattern Matching lets you work more efficiently, focusing your efforts on the most pressing problems. This, in turn, translates to faster time-to-market and a competitive edge in the rapidly evolving semiconductor industry.
Shift-left Calibre Pattern Matching improves verification workflows, reduces unnecessary design iterations and improves the overall quality of IC designs. Interactive, code-free verification use models allow designers to validate their work in real time without waiting on rule development or deck changes. By catching symmetry issues and IP placement errors early, you can rest easy knowing IP blocks exist as intended and where symmetry is required it actually exists.
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