The message is clear, but who’s actually receiving it is rather murky.
Looking around the system-level design industry from the vantage point of DAC is like looking down on a bustling city from an airplane. It’s impossible to see all the different processes and technologies that go into creating a design from too high up, just as it’s almost impossible to see the entire system-level design from a single gate or memory subsystem or block.
That’s the whole purpose behind modeling, which increasingly is where the industry is headed at advanced process nodes. Models ranging from TLM 2.0 to networks on chip and methodologies like VMM and OVM allow us to get the job done by managing lots of little pieces. The problem is that you have to think at the upper level, when most of the work has to be done at the nano level.
This is pretty much a slam dunk for recent engineering school graduates. They work with the tools that were given to them by their professors. But they lack the granular knowledge to fix something when it goes wrong or to be able to think of unique ways out of a problem when it’s not included in the model.
On the other hand, the engineers who have been doing designs for a decade or more understand lots of little pieces but they’re reluctant to use the new models. Modeling implies surrendering some control to the greater whole, which is not something that comes naturally to most people. Worse, engineers who have kept that kind of hands-on approach in the past generally have come up with better designs.
But times are changing, and we are at a crossroads in design. Engineers need to think differently at 32nm than they did at 130nm. Chipmakers need to invest in the necessary skills and training if they to produce great designs, rather than just hiring young graduates for less money, and tools vendors need to educate the chipmakers as an industry rather than just preaching their message to devotees of design at DAC.
–Ed Sperling
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