Relocating Intelligence

For the past couple of decades, intelligence in a system was largely a function of the logic in a processor. That may change, given some of the disparate discussions now under way across the electronics industry.

Putting all the intelligence in one place can make the design process more efficient, but it doesn’t necessarily make the system more efficient, either from a performance or power standpoint. That doesn’t mean the central brain of a computer should give up overall management, but it does mean some of the decisions may have to be localized.

And yes, before I get pummeled with criticism, there has always been at least some embedded logic in certain areas. But just like corporate re-engineering in the 1990s, where companies like Accenture and McKinsey told executives to move the decision-making closer to the customer, the same has to happen in the semiconductor world. More decision-making needs to be discrete, with less of actual yes or no decisions made by the system processor.

What makes this approach intriguing are two relatively recent developments. One is power and performance. Localized decisions are quicker, require fewer processor cycles and can be done over shorter distances. The second is a function of physics. No one can build a chip with a powerful enough single core anymore to ensure that certain decisions have priority. And with more regular structures at 32nm and beyond, there’s no such thing as back-wiring or workarounds. You now have to design within the structure if you ever expect to get it verified and manufactured.

That calls for a different focus on the way intelligence is designed into a system, how it is distributed, the communication fabric between the various processing centers, and how information is prioritized. This is the same kind of challenge that many of the software engineers are working on now, namely how to parallelize applications. But for systems to really be optimized, the intelligence also has to be parsed out and parallelized, ultimately into different sized cores with different performance metrics. This is no simple task, but it could provide significant performance breakthroughs for far less power.

–Ed Sperling