Resetting Serial Memory When A System Failure Occurs

Stability is an important consideration in embedded design, but electronic systems can suffer malfunctions triggered by a myriad of root causes. These include poor signal integrity, power spikes, software errors, and erroneous user interaction, just to name a few. These anomalies, in turn, can lead to inconsistent system operation or can even cause the system to hang.

Although the list of possible root causes may be impossible to quantify, resetting the device is often the first way to address such issues. In many applications, where resetting the device is straightforward, it is a mere inconvenience – but reset can be a huge challenge when it comes to embedded systems.

The challenge of reset in embedded systems
Embedded systems must run as continuously as possible with minimal downtime. These systems are often inaccessible and must autonomously recover from failures. While such systems make use of built-in supervisor mechanisms to detect and recover from failures (for instance watchdog timers), such mechanisms don’t always cover every possible failure scenario.

Design engineers want to ensure that all devices in a system are set to a known state at power-up and that all devices in a system can be reset to a known state in the event of an error condition or on a reboot command.  A soft reset of the system can also be part of an error recovery strategy, and it’s important that the system as a whole is able to reset all components and subsystems to a known state.

Resetting serial flash
Reset can be a particular challenge for memory manufacturers, who today are under pressure to reduce pin counts and produce smaller, lower-cost packages which often do not have a dedicated reset pin. Even if they do have a reset pin, it can often be difficult to use because the same pin serves multiple functions.

This presents a challenge to designers, but there is an answer. Serial flash devices that support the new JEDEC serial flash reset protocol, defined in the standard JESD252, can overcome the challenge.  The standard defines a mechanism which enables control of the reset function without needing a dedicated reset pin.

As an alternative to a reset pin, JESD252 uses the Serial Peripheral Interface (SPI) signals – clock, chip select, and serial data – to transmit a sequence that directs the device to reset itself. During this reset sequence, the clock signal is held low to differentiate the reset transaction from a basic SPI command, and preclude other SPI commands from being sent. The chip select signal is used as a clock for the recipient device. To prevent erroneous resets caused by noise, a specific sequence of transitions is transmitted on the data pin.

Getting more bandwidth from the SPI
SPI is widely used to connect MCUs to peripherals and memory devices in embedded systems, and it is often used for serial NOR Flash that stores executable code.

SPI Interface

To achieve more bandwidth from the original SPI specification (which had just a single signal for data-in (MOSI) and Data-out (MISO)), employing four (QUAD) or eight (OCTAL) bi-directional data signals is a way of enabling more data bits to be transferred on each clock cycle. These expanded SPI (xSPI) interfaces are defined by JEDEC in JESD251 and are used in many new MCU devices today where eXecute-In-Place (XiP) – code is executed directly from the serial memory – is becoming the new standard.

XiP not only provides high performance, it also supports instant-on, while keeping power consumption to a minimum. In addition, material costs are reduced because less SRAM is required to execute code.

When code is being executed directly from the serial flash as it is in XiP operation, resetting the memory along with the MCU in the event of a system failure is now critical to ensure a complete and full system reset. It is essential to ensure the MCU and memory are fully synchronized and all components boot from a known state. This is what makes this JEDEC reset very important indeed.

Building better designs
Today’s Octal xSPI memories, such as Adesto’s EcoXiP, deliver the necessary performance needed for XiP operation. With EcoXiP, Adesto was the first manufacturer to ship serial NOR flash memories that support JESD252. EcoXiP features an Octal SPI interface to provide higher performance than Quad interfaces. The JEDEC Reset is also included in Adesto’s new FusionHD AT25XE321B Wide VCC ultra low power SPI, DUAL and QUAD I/O devices.

Designers can achieve greater customer satisfaction by incorporating serial Flash memory devices in their designs that support the JESD252 serial reset protocol, with the ability to develop more reliable and stable products.

Using XiP, they can deliver the performance needed at lower power and less cost. While XiP requires a compatible memory interface on the MCU, a growing number of manufacturers are providing support for such an architecture.

Learn more about how EcoXiP supports instant-on and boosts performance by executing sequential instruction fetches without the need to send an address for every read.