RISC-V Unleashes Your Imagination

Since October 2020, Renesas has been officially active in the RISC-V microcontroller space and successfully launched two ASSP products, for motor control and voice-driven HMI systems. Now a general-purpose MCU enhances the RISC-V portfolio. It is the first MCU using a RISC-V core developed internally at Renesas.

The R9A02G021 general-purpose microcontroller features an interesting mix of analog and digital peripherals, as shown in the block diagram below.

Fig. 1: R9A02G021 RISC-V MCU block diagram.

The device has a generous program memory of 128KB which supports well in-field updates, thanks to the small erasable block size granularity of 2KB, and the capability to swap the initial 16KB startup section for implementing an updatable user bootloader code. To make the update process even more reliable, a flash shield function preserves areas from accidental erasure and the protection can be made permanent.

For software IP confidentiality, a flash read protection function allows the user to define a memory area to hold program code which can only be fetched for execution but not read out as data. This effectively creates an executable section that is protected from simple copying. Production control can be implemented using the Unique ID (a read-only device unique serial number, programmed at the Renesas factory) and the User ID, a 64-bit user-defined value. The User ID can be programmed by the customer in production inside a hidden memory area and becomes readable only if the application image holds a certain ‘unlock key’ value in a user-defined memory location. In this way, you can make sure that only legitimate applications will have access to the confidential value, which could be used further as a seed for authenticating external agents, generating data encryption keys, etc. In fact, a true random number generator hardware is embedded to support such simple but effective use cases.

The 16KB on-chip RAM is well dimensioned to provide the peripherals with data buffering space and hold all application variables required. Almost the whole SRAM is protected by parity bits, and for enhanced reliability 4KB are protected by an ECC code able to correct single and detect double bit errors. This is the place to store application-critical variables that need to be additionally secured from accidental environmental modifications (for example the ever-present cosmic radiation particles).

Application parameters and runtime information status can be stored in a non-volatile data flash memory of 4KB, erasable 1KB at the time, that can even be used to emulate an EEPROM.

Looking at the system performance, the Renesas RISC-V CPU is achieving a baseline CoreMark score of 3.27CM/MHz already on an open-source compiler, whilst other professional toolchains can even improve that further (watch for more scores to be published on the EEMBC website in future). The RISC-V instruction set architecture (ISA) is ideal to optimize the CPU implementation and Renesas has taken care of adding several extensions which are very important for deeply embedded systems. The multiplication and bit manipulation extensions, and the built-in hardware divider, accelerate operations since the same results can be achieved with fewer instructions. The additional compressed instructions further contribute to code size reduction, faster execution, and power saving as the number of flash program fetches is reduced.

The CPU has also built in a dynamic branch predictor which observes the program flow and can choose the most likely path being taken during a branch so that the next instruction can be executed without interrupting and flushing the pipeline; this improves the total number of instructions per cycle. With all these CPU features combined, users can develop a very performant application in a compact device.

Overall, having developed our own CPU core enables Renesas to optimize the implementation, gives full control of the design choices, and secures the IP roadmap for future products. Renesas has historically deep experience in implementing CPUs for microcontrollers. This provides customer assurance on the deployment of commercially viable products, supported by renowned Renesas quality, and eliminates any concerns about proprietary architectures.

Raw performance would be meaningless without enough I/O interfaces. This device has a well-balanced set of analog and digital peripherals to realize mixed-signal applications at a lower cost since many building blocks are already embedded in the MCU. For example, on the analog side, there is a 10-channel 12-bit A/D converter (ADC), a 2-channel 8-bit D/A converter (DAC), two comparators, and an on-chip temperature sensor. The ADC and comparators can be used over the whole operating voltage range of 1.6V to 5.5V, and the ADC can also input an external voltage reference, which makes it easy to adapt best to the application needs.

The digital connectivity portion supports many protocols like UART, SPI, I²C, and even a dedicated remote control interface. Battery-operated applications are covered by the excellent standby current consumption of 300nA with all SRAM contents retained. In this condition, the application can quickly resume operation in just 4µs, ready to react to the external wakeup event. Long standby times can be achieved by means of a real-time clock or the internal 32-bit low-power timer. Applications that focus on reliability will benefit from the application watchdog, a second clock-independent watchdog, a CRC unit, a clock monitor, and the ADC self-test logic. Even the operating temperature is not a concern, because the device can operate up to a 125 °C temperature without restriction.

Starting with a new architecture is never easy, especially when used to working with the dominant legacy and proprietary architectures established in the market. It may feel like a large commitment of time and effort to study the intricacies of the differences, and for the pragmatic among us, to grab some test platform and configure a suitable tool environment to explore and try things out. This is why Renesas provides a full-featured set of free-of-charge tools. The Eclipse-based e² studio IDE includes a code generator plugin, an LLVM-based compiler, and a debug environment. All the building blocks required to start testing a project! You can also start looking at many application notes with example projects already available and more on the way.

Our Fast Prototyping Board is low-cost and ready to be expanded with sensing, display, and connectivity functions. Do you have some Pmod, Arduino, or Grove add-on modules? Grab them and start experimenting! The onboard SEGGER J-Link enables you to kick-start testing your project with just a USB-C cable. Note that the same connection can also support a virtual UART-CDC channel so you can implement a debug console or a control terminal for your application.

The tool bundled with the e² studio environment is called Smart Configurator. It can set up and generate the configuration code for IOs, clocks, system settings, and even low-level hardware driver APIs for the peripherals. You can get a complete project generated with just a few mouse clicks.

Commercial IDEs like IAR Embedded Workbench or SEGGER Embedded Studio already support the Renesas R9A02G021 in their RISC-V edition. The Smart Configurator is also available standalone and can generate projects for those IDEs to ensure a smooth transition. What’s more, SEGGER provides a special discount for Renesas users developing on the R9A02G021 MCU, please refer to the Embedded Studio software page for more information.

RISC-V, the emerging free and open ISA, is enjoying a lot of momentum within the engineering community. This MCU provides a platform to introduce this exciting and promising technology into your products. Get one of the kits and start your RISC-V adventure today!