New Risk Factors For SoCs

By Ed Sperling
Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips.

But there are also plenty of landmines in IP integration, and there is a growing concern about how best to avoid problems that can affect performance, power, or even the integrity of an SoC. This has led to a slew of tools being created for analyzing IP, integrating it—the whole network on chip concept was created for this purpose—and verifying and testing that it all works together. Efforts are under way to improve the integration process and help standardize the characterization, as well.

Still, there is still plenty of concern about just how well all the pieces go together. In his keynote speech at the Intel Developer Forum this week, CEO Brian Krzanich said that third-party IP can be added into the company’s Atom line and its new Quark chips—the company’s latest offering for the Internet of Things. But Intel is still going to be very hands-on with the integration and manufacturing of those chips and plans to be “a good supplier” using its “Copy Exactly” strategy for identical equipment, methodology and process technology across all of its fabs.

This is more than just a business proposition to grab all the manufacturing revenue—although that appears to be at least part of the motivation. The other part is that integrating IP isn’t so simple, and it’s getting harder at each new process node, which is why there has been more integration of software into hardware companies and more IP into subsystems that include both.

Synopsys, which has been building its own subsystems, now puts services teams on site at major chipmakers to help facilitate the integration of IP. And Cadence has been adding programmability into some of its IP to simplify this process. But it’s not just about electrical engineering anymore.

Unexpected pitfalls
One of the real shockers when it comes to IP integration has nothing to do with engineering at all. It involves government regulation of what can be sold where—which is an extended supply chain issue. This is particularly true for analog IP, but it also can affect digital IP depending on how it’s being used, in what types of products, and which countries those products are being sold into.

“With IP, everything you sell has to be in accordance with government regulations,” said Larry Diesenhof, group director for export compliance and government relations at Cadence. “DDR controllers are not regulated, but analog to digital converters are. So if they’re restricted, and you put them into a product, you can’t ship that product to certain countries.”

The list gets far more granular than that, too. In the 1990s, the bulk of the U.S. export regulations involved the sale of computer technology to China and Russia. Fast forward to the present and IP may be okay to include in a TV remote control but not in a high-level machine tool. And missile technology might be okay for sale to South Korea, but not to Israel.

“We’ve been working with product marketing people to get a handle on this before they start development,” said Diesenhof. “You also need to make sure who you sell to is reputable. If it doesn’t feel right, ask questions.”

There are other regulations to consider, as well. There are multiple iterations of the regulations for hazardous substances—notably lead, cadmium and other heavy metals—as well as restrictions on so-called “conflict minerals.”

“For a long time we believed that everyone in the supply chain had good intentions,” said Bernard Murphy, chief technology officer at Atrenta. “We’re seeing the end of the age of innocence. The channel can be corrupted.”

This is particularly troublesome when it comes to security, where there are no tools available to automatically do an electromagnetic analysis of the IP. “The underlying process is lacking even before you think about tools,” said Murphy. “And then, you have to figure out what the IP is going to be used for. It’s difficult to put that burden on an IP provider. It’s like banning nitrates because they can be used to build bombs. For most people, they’re used for fertilizer.”

Power and performance issues
Far better understood by engineering teams—although certainly no simpler to deal with—are the electrical and physical effects of IP. The quest for more functionality with higher efficiency now includes both hardware and software engineering teams.

“Understanding power consumption of these IPs is essential to meet the overall power budget of the SoC,” said Arvind Shanmugaval, director of applications engineering at Ansys Apache. “The responsibility of power lies on both the IP provider and the customer. IP providers should be able to capture proper models for their IPs in a format that can accurately represent the power for the various operating states. Conversely, the customer should be able to use these power models effectively in power estimation simulations.”

This is a lot easier said than done when it comes to ensuring power integrity inside IP, as well as validating that IP within the context of a complex SoC. In the past, a model that captured the power number for IP was used for power integrity verification. But with IP now sharing power domains and multiple operating states, time and space need to be added into the list of things that can affect current distribution, making verification significantly more challenging.

“It is still common to see SoCs blowing their power budget due to poor architectural planning or selection of IPs that don’t meet the power spec,” said Shanmugaval. “In addition, material properties have not been much of a concern for semiconductor manufacturing recently. However, shrinking geometries in advanced process node have caused the electromigration (EM) limits to decrease rapidly. EDA tools have always been able to model EM failures for ICs. The challenge recently has been both the decreased EM limits along with the complexity of the EM rules associated. Highly accurate analysis using transient approaches along with advanced rule handling is now mandatory.”

Stacked die will add another dimension to this problem—literally and figuratively. Thermal issues will become more of an issue in stacked die, but they already are becoming an issue for wearable electronics—particularly devices such as Google Glass where heat next to a person’s head will be extremely noticeable. Less obvious is the effect of increased bandwidth on noise, which will affect the integration characteristics of IP. Wide IO and through silicon vias will improve throughput to memory, for example, but it also will increase noise in the device.

“Technologies such as Chip Power Model (CPM) can model power noise behavior of the entire die in both frequency domain and time domain seen through the TSV connection points,” said Shanmugaval. “We could also see technologies such as RTL power model (RPM) being used to model cycle accurate power for entire dies. The possibilities are limitless when creative.”

But new possibilities also create more challenges for integrating IP. And those challenges will only grow as features shrink, new architectures are introduced, and with tighter integration of hardware and software. Integration of IP is turning into a multidisciplinary, multi-faceted and multi-dimensional problem, and all of this will have an impact on time to market, power and performance, and ultimately the cost of developing and building new SoCs.