Robust Variation-Aware Smart Power Designs For Silicon Success

Power management ICs (PMICs) is a rapidly growing segment in the semiconductor industry. The growth has been fueled by the demand for Smart Power applications that include wearable electronics, mobile computing platforms, printers, hard disk drives (HDD), IoT devices, and the full array of automotive applications. According to a report from market research firm Coherent Market Insights, the global PMIC market is expected to grow to USD $5 billion by the end of 2027, with a CAGR of 5.3 percent during the forecast period (2020-2027).

There is currently a massive wave of new smart power applications where PMICs play a significant role, specifically in the area of combating climate change. This is most apparent with the influx of electric vehicles, eco-friendly manufacturing plants and renewable power sources to reduce CO2 emissions.

Fig.1: Use of power management ICs for smart power applications.

One underlying silicon process technology for many of these Smart Power applications is BCD (Bipolar–CMOS–DMOS). Invented by STMicroelectronics, this super-integrated BCD silicon gate semiconductor process technology combines the high-precision analog transistors of a bipolar process, the high-performance digital switching transistors of a CMOS process, and high-power DMOS transistors on a single chip to serve complex applications. Several leading semiconductor companies use BCD for their power management IC products.

Fig. 2: BCD silicon process platform. (Source: STMicroelectronics)

The choice in the type of silicon technology used, coupled with optimal power, performance, and area (PPA) metric, drives the market competitiveness of PMIC products for smart power applications.

Verifying the building blocks of PMIC

Verifying the precise operation of the building circuit blocks is vital to ensuring specifications are met. The circuit blocks could include functions such as DC to DC converter, bandgap reference, power sequencing, etc. These functions are essential in most analog circuits and smart power applications. They are widely used for power supplies, analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and other circuits used for control systems. Design teams must simulate the circuit design blocks across process variation and environment conditions to ensure they will operate correctly. Robust verification of these circuit blocks necessitates high-sigma analysis to account for all design variations and meet power, performance and area requirements to achieve high yielding ICs.

Variation-aware verification challenges

Traditional variation-aware verification solutions are not scalable and accurate enough to meet production design quality and schedules. To adapt to design complexities and meet the stringent accuracy requirements, designers have to perform extensive process, voltage and temperature (PVT) and Monte Carlo SPICE simulations. This enables them to account for all potential design variations. However, running tens of millions to billions of traditional brute force Monte Carlo simulations is slow and expensive.

Alternatively, design teams have been using shortcut approaches, such as running a smaller set of Monte Carlo simulations and using extrapolation techniques. This is susceptible to producing inaccurate results, leading to silicon failures.

Design over-margining is another option design teams consider. This comes at the cost of suboptimal design performance, impacting the quality and market competitiveness of the smart power end product.

Uncovering potential design failures

Debugging the root cause for potential design failure is time-consuming, but necessary, to avoid serious consequences. Designers need to be able to quickly find potential design weaknesses, iterate, verify the design quickly and accurately, and measure the impact of statistical process variation on the design’s performance. This enables design teams to make intelligent design tradeoffs and adjustments to meet performance specifications.

An essential task in the debug flow is to be able to visualize the sensitivity of the design to process variation. This includes sweeping device sizings at worst-case PVT and statistical corners. In addition, identifying the specific device(s) causing the most variation aids the designer in making decisions on where to make the design adjustments to achieve the target PPA and ultimately silicon success.

Standardizing on a robust variation-aware design and verification

Siemens EDA’s Solido Variation Designer provides a variation-aware software solution using machine learning to deliver speed, accuracy and variation coverage. It consists of a comprehensive suite of tools for variation-aware design and verification. Designers have the flexibility to select the best tool based on the design type, design phase, targeted accuracy and sigma requirement.

The Smart Power team at STMicroelectronics standardized on a robust variation-aware verification flow using a combination of Solido Variation Designer tools: PVTMC Verifier and High-Sigma Verifier. The PVTMC Verifier tool provides full sign-off level verification coverage across process, voltage, temperature (PVT) and Monte Carlo (MC) variation that is 1,000X faster than brute force simulation. In addition, it identifies the worst-case corner for any target sigma and finds design sensitivities to variation.

The High-Sigma Verifier tool is the next-generation high-sigma verification technology. It quickly verifies any circuit to high-sigma intelligently with perfect Monte Carlo and SPICE accuracy. Figure 3 shows a sample of high-sigma results. Furthermore, it finds rare failure modes automatically.

The white paper “Robust bandgap circuit design enabled with a fast and accurate variation-aware verification” illustrates how the Smart Power team at STMicroelectronics debugged and performed a thorough and accurate verification of their bandgap voltage reference circuit and achieve a yield greater than 8 sigma.

Fig. 3: A sample of high-sigma results.

Summary

Designs for Smart Power applications require high-sigma verification for full variation coverage to achieve high-yielding silicon. Traditional verification approaches are not scalable and accurate enough to meet production design quality and schedules. Solido Variation Designer uses machine learning to provide SPICE accurate and verifiable high-sigma verification with orders of magnitude speedup. This enables power management designs with better performance, lower power and smaller area.