Learn more about a design-for-power methodology, from early in the design process at the RTL for maximum impact on power.
This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.
To download this white paper, click here.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Foundry forms ASIC subsidiary as it focuses on 14nm/12nm and above.
Market overcrowding, more efficient manufacturing, and growing list of scaling issues create a challenging competitive landscape.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.
Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?
Assessing the reliability of a device requires adding more physical factors into the analysis, many of which are interconnected in complex ways.
Continued integration is no longer the natural way forward for semiconductors. What needs to happen to make it easier?
Improvements in power, performance and area are much more difficult to achieve, but solutions are coming into focus.
Shift to cloud model has kept power consumption in check, but that benefit may have run its course.
Edge compute covers a wide range of applications. Understanding bandwidth and capacity needs is critical.
In-chip monitoring techniques are growing for automotive, industrial, and data center applications.
Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.
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