A method for estimating from RTL descriptions of complex circuits.
This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change in fault coverage while considering various changes to a design. The technique automatically takes advantage of available designed in test logic and may be applied to either combinational or sequential test generation tools.
To download this paper, click here.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply