RTL Optimization Best Practices Help To Achieve Power Goals And Identify Reliability Issues Earlier

Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality and higher performance in SoCs is rapidly stretching power budgets to their breaking point. Power must be considered at every stage of chip design. Waiting to address power until late in the design cycle – post-netlist or during physical implementation – can be extremely costly. The design may overrun the power budget, overheat, or have long term reliability issues that cannot be addressed at the gate level, during layout or even package selection. The best point in the design cycle to address power is at the beginning, during the architectural and RTL creation stages. The earlier power analysis and optimization starts, the more likely a chip will meet its power objectives.

Traditional gate level approaches to reducing power are limited in scope. Downsizing gates at the netlist level can only accomplish so much. To achieve material gains in power efficiency, RTL designers should address power consumption and optimization from the very outset.

Leveraging best practices for low-power RTL design can help teams achieve low-power, energy efficient designs without late-stage surprises. Dealing with power at each stage of RTL design can help teams find power issues earlier and fix them faster. Power can be continuously measured and tracked throughout the RTL design cycle and power optimization tools can help quickly find and fix power issues while the RTL is still being developed.

There is no “one size fits all” approach to low-power RTL design, and each stage of the RTL development cycle has different requirements. Early RTL presents a unique challenge of incomplete functionality and no test vectors. As the RTL matures, RTL designers want to explore microarchitectures that optimize power. Power could be wasted due to redundant toggles that are functionally not needed. Identifying the sources of such redundant toggles and eliminating them can save substantial power. Mature RTL with power qualified vectors needs fine-grained, precise interventions to scrub power.

Power issues can also be discovered later during the SoC integration process when real workloads are used instead of synthetic workloads. Feedback from SoC designers to RTL IP designers can help fix the gaps and nip issues in the bud in time. Best practices for low-power RTL design span from early RTL to RTL freeze, IP to SoC and synthetic vectors to real workloads.

In this virtual seminar, on November 21^st at 8AM PST, participants can learn best practices for applying RTL power optimization. These practices are essential for realizing low-power, energy efficient designs, and can help you meet power budgets, mitigate potential reliability issues arising out of power and discover thermal issues early to take corrective action. NXP will present their perspective on applying these techniques. Participants will learn how NXP uses Siemens EDA’s PowerPro low-power design platform to simplify low-power design for RTL designers and how PowerPro allows coarse as well as fine grain power analysis and optimization to achieve truly low-power, energy efficient designs.