A look at the challenges and future direction of heterogeneous integration in the post-Moore’s Law era.
The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithography solutions. The demand for higher performance, smaller form factor, denser integration, and lower-cost devices is increasing more than ever due to significant progress made in products and services developed for consumer electronics, mobile devices, cloud computing, automotive, and various other applications. While the semiconductor industry continues to advance scaling of the integrated circuits, it is also turning to advanced packaging technologies to increase performance and integration while lowering costs.
One of the several challenges in heterogeneous integration is to bridge the gap in the I/Os available at the die level and the board level. At the die level, the trend has always been shrinking die sizes with increasing I/O density, so creative packaging technology is required to connect the dies to the board at such high I/O densities. Numerous evolving packaging technologies play a role in heterogeneous integration of devices, amongst which wafer-level fan-out (WLFO) packaging technology has been emerging as a dominant process. The WLFO process has been commercially deployed for several years with simple single-die designs, a single redistribution layer (RDL) on one side of a reconstituted wafer, and sparse silicon areas on thick reconstituted wafer profiles that resulted in thicker packages.
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