At 45nm and beyond, you can’t just design the chip and then think about the package.
By Ann Steffora Mutschler
After decades of being considered almost an afterthought, semiconductor packaging is emerging as an integral part of the Moore’s Law road map.
Power, heat, manufacturing and impurities like soft errors have become so pronounced at 45nm and 32nm that they are actually beginning affect the package. And while these problems are not new, continual shrinking has made them far worse. “As layers get thinner, there is less material to be consumed, so the problems are evident sooner,” said Richard Crisp, director of semiconductor technology at packaging technology provider Tessera.
The key thing at 45nm and 32nm with microprocessors and FPGAs — high power chips are the early adopters of that technology — they generally are going to have a lot of leads on them; typically with flip chip-type packaging, he said.
Intel is the undisputed leader at these advanced process nodes and has stated publicly that it employs a low-k dielectric in its advanced manufacturing nodes. Not to be confused with high-k, which is used for the gates at the transistor level, the low-k dielectric sits between the copper wiring layers on the chip. The low-k material is generally porous and very fragile, much like pumice stone that can be crushed easily. This fragility impacts the packaging, which must be considered when handled in the manufacturing process to avoid damage.
When a low-k dielectric is used with the standard wire bonding technique, the material under the bonding pad must be chosen carefully because the standard bonding force may crush and crack that dielectric, which could lead to reliability problems. “What’s been done is that people change the design rules and require structures made out of copper underneath the bonding pad,” Crisp said. “Instead of having an area to just route signals, we have to put in what is essentially a bunch of posts or pillars.”
On the other hand, if flip chip packaging is used, which involves putting solder bumps on the die, heat can cause issues with low-k dielectric. Because the industry has been shifting away from lead for the solder bumps to non-lead-type materials, there is an opportunity to ratchet down the melting point of the solder by changing the type of materials. In addition to that, when the die is cut apart on the wafers, the sawing process tends to leave behind a rough edge.
Historically, these rough edges around the edge of the die haven’t been a problem, but with low-k dielectric the roughness can form a propagating crack that will act like a zipper across the whole die. As a result, structures have been added to the scribe area in between the die area on the wafer to resist the propagation of the cracks, which also helps with the heat tolerance for the flip chipping.
Another problem that comes up with 45nm and 32nm geometries is electromigration of the copper. Particularly with flip chip attachment where solder is being applied to the die, the tin in the solder can diffuse and form intermetallics, which can result in reliability issues because when current is run through it. Sometimes there are voids where the tin had flowed from and it leaves a hole behind. These voids in the metal conductors increase current densities. Solutions to this problem include using copper bumps on the die instead of just putting the solder directly on the die such as underbump metallization (UBM) structures, but different companies use carefully-guarded proprietary methods to deal with the problem.
Thermal issues have been and continue to be an issue for packaging at advanced nodes, particularly for microprocessors and FPGAs. Intel’s desktop processors, for example, can have power dissipation of as high as 150 watts, and typically are in the 80 to 120 watt range. As such, heat continues to challenge the packaging industry to find a way to get the heat out, while package makers keep striving to develop thermally enhanced packages. The move to flip chip is helpful because some heat conduction can happen through the bumps, into the substrate and into the PCB.
One trend that’s sure to gain interest is 3D packaging, which makes sense particularly for microprocessors.
“Intel has found that instead of just cranking up the clock rate, what makes more sense when they go to a newer process node is to maintain a modest clock rate, but put more cores on the die,” said Crisp. “They’ve done a lot of analysis to show that it is a more efficient way to scale. One of the things about adding the cores is that each one needs its own memory to operate on, so instead of scaling the clock rate you’ve added a lot of parallel computing resources, each of which is demanding memory bandwidth. So the problem now is that you’ve got to figure out a way of getting a huge amount of memory bandwidth in and out of this processor die. They’ve quoted numbers on the order of a terabit per second of bandwidth. There are a lot of different ways to supply a terabit per second such as narrow buses that have very high speed signaling and that’s okay, but when you start working through the details you pretty quickly come up with 25 to 30 watts that you’re going to need to drive that I/O interface and you’re going to need something like 600 signal leads. And that’s not very attractive. There’s got to be a better way.”
That other way is to stack the memory die directly on top of the processor die and interconnect them with through silicon vias (TSVs), which allows the data links to be simplified. This method of 3D integration, in which chips are thinned, stacked and interconnected increase density and performance.
“The high-speed narrow buses are usually very complex to implement. They’ll contain phase lock loops, exotic drivers and terminated buses,” said Crisp. “But if you can keep the signal leads extremely short, then you don’t need any of that. You can actually run the wires slowly and you don’t need terminations, you don’t need phase lock loops or that sort of thing, and that’s a really good optimization to make. It saves a lot of power so that terabit per second memory bandwidth can be supplied using die stacked on top of the processor with 2 to 5 watts of power instead of 25 to 30 watts going through the package.”
3D packaging is still under development and expected to be seen first in CPUs because of the intensity of the problems to solve. At the same time, it is a fundamental change in the industry supply infrastructure, which may ultimately limit its adoption in the longer term. But several packaging experts still believe it is the way packaging will have to go in the future.
However, additional issues arise with this approach including the need to thin the die. Given that the low-k approach causes fragility, traditional thinning techniques can crush the fragile layers. Some solutions include the use of chemical etching, reactive ion etching. Alternatively, IBM and AMD are using silicon on insulator (SOI) technology, which uses silicon dioxide in the process; it is easier to perform the thinning because the chemicals used to etch silicon will not etch silicon dioxide.
Morry Marshall, vice president of strategic technologies at Semico Research, said IBM’s work with Albany Nanotech revealed that the real power hogs in DRAM are the high-speed interface chips, not the DRAM chips themselves. “They want to minimize the number of interface chips and put the DRAM really close together to cut down the inductive resistance so that less power can be used in the interface chip,” Marshall said.
In addition, the onboard cache will not be able to handle the proliferation of cores inside of chips. IBM and Albany Nanotech want to stack the SRAM to get additional SRAM using TSV technology, allowing it to get really to the cores to attain the needed speed.
“Past that is some kind of 3D system in package (SIP) using TSVs,” said Marshall. “That would be stacking logic, memory and interface chips all in one stack to reduce power, and volume. With a thinned wafer you could package it in a chip-scale package or a flip-chip package.”
In the meantime, the industry continues to push development of the technology along. A few organized industry activities focused on 3D packaging include IMAPS-International Microelectronics And Packaging Society (IMAPS)’s 3D Consortium initiative and Sematech’s upcoming Workshop on 3D Interconnect Metrology, which is being held July 15 in San Francisco during Semicon West, and the International Symposium on Advanced Gate Stack Technology being held August 23 to 26, also in San Francisco.
Helpful links:
International Microelectronics And Packaging Society (IMAPS)
Microelectronics Packaging and Test Engineering Council (MEPTEC)
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