tag: soft errors

Robust Latch Hardened Against QNUs for Safety-Critical Applications in 22nm CMOS Technology
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

A technical paper titled "Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS" was just published by researchers at Anhui University, Hefei University of Technology, Anhui Polytechnic University, Kyushu Institute of Technology, and the University of Montpellier/CNRS. Abstract: "With the aggressive reduction of CMOS transistor feature sizes, the soft ... » read more

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
By Technical Paper Link - 25 Apr, 2022 - Comments: 0

New research paper from University of Saskatchewan, with funding by NSERC and the Cisco University Research Program. Abstract "Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should be explor... » read more

FLODAM: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs
By Technical Paper Link - 20 Apr, 2022 - Comments: 0

Abstract "Modern technologies make hardware designs more and more sensitive to radiation particles and related faults. As a result, analysing the behavior of a system under radiation-induced faults has become an essential part of the system design process. Existing approaches either focus on analysing the radiation impact at the lower hardware design layers, without further propagating any rad... » read more

Using Static Analysis For Functional Safety
By Ed Sperling - 15 Jan, 2020 - Comments: 0

Fadi Maamari, group director for R&D at Synopsys, explains why static analysis is suddenly in demand in auto chip design, how it can help to choose the best implementation of functional safety approaches, and where it fits into the design flow. » read more

First Look: 10nm
By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

How Reliable Is Your IP?
By Ed Sperling - 12 Sep, 2014 - Comments: 0

Almost everyone who has bought a new smartphone, car, home electronics device or appliance either has experienced technical glitches that require a replacement or repair, or they know someone who has experienced these problems. The good news is that only a very small fraction of the electronic glitches or failures can be contributed to hardware design. Most of it is due to manufacturing vari... » read more

Dangerous Electricity
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice president and senior product strategis... » read more

Why Semiconductor Packaging Matters
By Ann Mutschler - 27 May, 2009 - Comments: 0

By Ann Steffora Mutschler After decades of being considered almost an afterthought, semiconductor packaging is emerging as an integral part of the Moore’s Law road map. Power, heat, manufacturing and impurities like soft errors have become so pronounced at 45nm and 32nm that they are actually beginning affect the package. And while these problems are not new, continual shrinking has made th... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy