Should Sign-Off And Implementation Be Separate Tools?

EDA vendors diverge on approaches as complexity grows at advanced process nodes; what do customers think?


By Ann Steffora Mutschler

In the last stages of design, how data is readied for manufacturing used to be relatively straightforward. Point tools were used to implement the design via a place and route tool then the design was “signed off” with physical verification software.

Sign-off is the gate the design goes through before it can go into manufacturing. The design must meet the qualifications of the foundry or manufacturing group (if it is an IDM) to make sure the design will match the resulting silicon. Sign-off-quality data is also used by EDA tool vendors to drive implementation tools.

The name of the game with sign-off is accuracy, which means an exhaustive analysis that will match silicon closely. Conversely, when constructing the design, implementation is all about tradeoffs, particularly during optimization stages.

The constraints that each of these processes put on the system are different. Implementation needs to be nimble, constructed on an infrastructure that lends itself to doing quick comparisons to make the design better and better. Sign-off needs to be very thorough and accurate. This is why signoff tools – because of the qualification, infrastructure requirements and accuracy requirements – have traditionally been separate from implementation tools.

While it seems straightforward, it is not. Each tool provider has a different approach, which generally fall into two camps: a single, integrated sign-off and implementation flow, or the traditional, separate point tool methodology.

“Sign-off quality data driving implementation means having the place and route tool access the actual sign-off physical verification (PV) tool, as without that there will be a high chance for correlation issues,” said Michael Buehler-Garcia, director of marketing for Calibre design solutions at Mentor Graphics. “The design team needs to be able to achieve their tape-out date but also be confident their foundry will be able to fabricate their design, as well as the fab that is receiving designs from multiple companies with multiple design styles. But it also needs to be able to manufacture them using the same baseline process. So sign-off quality tools are critical, regardless of whether they are integrated with place and route tools or positioned later in the design flow.”

Rival Synopsys believes that parts of sign-off should be brought into implementation, but this needs to be done selectively and in a controlled fashion. Saleem Haider, senior director of marketing for physical design and DFM at Synopsys, compares this to cooking with butter:

A little is good, but if you overdo it, it’s not healthy.

“It’s not very healthy in the case of putting all of the sign-off into implementation because sign-off is about the nth degree of accuracy, and if you use the nth degree of accuracy to drive implementation you end up with a system that is not very healthy,” said Haider. “It doesn’t move very fast, it is very lethargic and you’re not going to be able to get the design done. It will basically choke the system. While it is an interesting question of putting sign-off into the implementation tools, taking that approach can be very damaging to the throughput that the system is going to have.”

As a result, the company maintains two separately architected, separately optimized infrastructures. One infrastructure is optimized for the sign-off application and the other infrastructure is architected and built for the implementation side. Very tight links allow sign-off data to be selectively brought into implementation where needed.

“[This] contrasts so strongly with the traditional way of completing the design,” he said. “You think you’re done, so you hand it over for verification and, what do you know, there are some issues. It then has to be brought back into implementation, and the errors need to be fixed. It’s the surprise at the end at the very end which can be extremely damaging to schedules.”

Cadence, meanwhile, is taking a different approach. Dave Desharnais, group director of implementation and analysis/verification product management, noted that with a lot of the manufacturing effects that are happening…”if you’re designing with things that drive your timing-driven or power-driven or sign-off-driven implementation and you’re not actually using the sign-off tool to do that, then you have correlation issues at the back end.” As a result, he is seeing customers turning to consolidation – not for financial reasons — but for sanity reasons.

Put another way, he said, “Having sign-off in the loop or having sign-off driven implementation in the loop is a risk in some people’s minds because they want an outside, third-party point of view that’s not drinking the Kool-Aid. That’s something we discuss with customers all the time. At the end of the day, sign-off is sign-off.” Cadence takes the core engines from its sign-off category of tools and builds them into the implementation step, thereby redefining sign-off driven implementation.

“The difference between a traditional approach where you don’t have that happening is that you have coarse grain, which is faster because things have to be done in an optimization loop and so you can’t do a sign-off because it takes too long. Historically we have shied away from doing that because it’s a performance game. You can always fix it, tweak it, put in some margin, try to address it and correlate it at the end, but that’s becoming huge now so the difference is granularity level,” he continued. “What really helps here is if we can agree as professionals that sign-off is indeed sign-off no matter where it sits. And if it is sign-off and certified as sign-off, you can make it faster through efficient memory or multicore or whatever, and by that virtue actually have it be fast enough to be in the loop, why wouldn’t you?”

“Place-and-route tools consider physical design rules and some DFM criteria as they are creating a physical layout,” said Mentor’s Buehler-Garcia. “The goal is to eliminate all PV problems during creation of the layout so there are no design rule errors when the design is completed. However, this is not possible because many more detailed advanced checks address elements that are not considered by the place-and-route tools. For this reason, integration-to-sign-off tools are needed at all levels of the design-to-manufacturing cycle from layout editors used for IP creation, to place and route for SoCs, and to mask data preparation. As with all other parts of the design process, speed of verification is important, but not at the expense of missing errors or understanding what is going to be manufacturable by your target process.”

Mentor’s approach is multi-corner, multi-mode (MCMM) infrastructure which allows the implementation tool to concurrently optimize for any number of mode and corner combinations, explained Sudhakar Jilla, marketing director for place and route tools. He claimed that some customers are designing up to 50 to 60 mode-corner combinations at 40-nm.

The key to this is the timing engine. “Everybody claims to have it but fundamentally they are still using the same timer inside that used to work on one mode/two corners. It’s very difficult in the place and route system to rip out a timer and put in a new timer,” he said. Mentor holds a patent on the MCMM technology that covers what the company calls “virtual timing graph technology,” which allows the representation of any number of mode-corner combinations so that the tool can optimize any number of mode-corner combinations.

In the end, the customer doesn’t really care about the underlying technological approach. What they do care about is getting to tape-out in the fastest manner possible without one thing saying “X” while another is saying “Y.” They’ve got bigger things to worry about, particularly moving down to 45- and 32-nm, when other issues start to crop up such as controlling leakage power in the implementation flow.

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