SoC Assembly And IP Reuse

I had the honor and opportunity to present at the 2014 Electronic Design Process Symposium in Monterey last Friday. This annual workshop is run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation.

There were more than 30 participants each day. Most of them very experienced people with lots of technical and business responsibilities. It was very interesting to spend two days discussing issues with industry heavyweights like Wally Rhines, CEO of Mentor Graphics, and Martin Lund, senior VP of the IP group at Cadence.

The second day of the workshop featured the Integration, Designing and Standards track where Patrick Soheili (eSilicon), Warren Savage (IPextreme) and I presented our views on what is required to efficiently assemble systems-on-chip (SoCs). Patrick’s presentation focused on DFY and backend physical implementation issues (naturally) while Warren and I focused mostly on the front-end architecture and IP integration processes.

Surprisingly, Warren and I had very similar observations and guidance for chip development teams, but our opinions were based on very different perspectives.

Warren is often brought into companies from the outside to help them solve their IP reuse and SoC assembly issues. An “outside-in” point of view is often needed to tell truth to power, and that’s what Warren does. I based my talk on the lessons learned from working within our SoC-maker customers. This is more of an “inside-out” point of view.

Warren and I both concluded that the success or failure of a successful IP reuse and SoC assembly strategy is PEOPLE.

We talked strategies, systems and best practices, but the bottom line is that a company culture usually has to change to be able to share chip architectures, IP, tools and processes throughout the corporation. This is what is required to make the best economic use of a company’s resources. The companies that do this the best turn out more chips at lower cost. And they can more quickly respond to “market misses.”

I sensed disappointment from a couple participants that we didn’t discuss more about tools and focused on principles. However, I felt it would have been a waste of time to talk about the pros and cons of IP-XACT, Perforce, SVN, UVM, requirements traceability, etc. without addressing the elephant in the room: People.

The graphic above gives you a peek at one of my slides. Yes, it was meant to be a little intimidating!

You can download the complete presentation, titled “Best Practices for SoC Design,” here.

Please let me know what you think.

P.S. Many thanks to the organizers of this IEEE workshop:

• Aparna Dey (General Chair and Technical Marketing Director for Standards at Cadence).
• Naresh Sehgal (Session Chair for Pre-Silicon SW Development Platforms and Software Architecture Manager at Intel).
• Gary Smith (Session Chair for Top Semiconductor Design Flow Challenges Panel and founder of Gary Smith EDA).
• Herb Reiter (Session Chair for FINFET, 3D-IC, FD SOI and head of eda2asic consulting).
• Daniel Nenni (Session Chair for 2 tracks! IP Verification & Qualification and Integration, Designing, Standard. And Chief SemiWiki dude).
• John Swan (Past general chair and Mother Hen, making sure everything was running well. He runs Swan on Chips.)