SoC Electromagnetic Crosstalk: From A Tool Perspective

Why most of the commercial electromagnetic solvers and extraction engines are not suitable for analyzing EM crosstalk in a typical SoC design.

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Most commercial electromagnetic (EM) solvers are limited by the size of the design that they can handle, or they may take a very large amount of time or memory to perform the task. These capacity, memory or runtime constraints often lead to dropping important details about the design and the surrounding environment, which in many cases can mask the effects of EM crosstalk, or can lead to the wrong conclusion. For a tool to effectively tackle EM crosstalk challenges in today’s SoC designs, there are several key requirements:

•   Ability to identify Victim/Aggressor net pairs that most likely exhibit EM crosstalk. This is very important because analyzing all possible pairs of aggressive/victim pairs is not feasible. Hence it is highly desirable to have a mechanism for quickly evaluating the design layout and to rank order the most likely candidates that need to be analyzed.

•   The engine used for the extraction and EM solving must be able to handle the capacity associated with large design partitions and to efficiently utilize the memory of the compute infrastructure available.

•   Maintaining accuracy is vital when performing EM crosstalk analysis, however, extreme levels of detail may only be needed in critical parts of the layout and not everywhere. Hence, it is often necessary to automatically operate in a hybrid extraction mode (hybrid meshing) to achieve high-accuracy while maintaining reasonable modeling/extraction speed.

•   Must operate across design hierarchies to be able to analyze potential EM crosstalk issues across various design blocks.

•   It is very important to efficiently model all types of surrounding structures (power/ground nets, substrate, coupling caps, bond pads layers, package layers, seal ring, scribe lines, etc.).

•   In advanced technology nodes (16nm and below), the tool must handle layout-dependent biasing, resistivities and thicknesses. Ignoring these layout-dependent effects (LDE) can impact the quality of the extraction and can lead to erroneous results.

•   Generate different output models, various types of analysis and simulation. A key requirement is to produce a physical RLCK netlist. The size of these netlists can be enormous, hence it is crucial to reduce the model size without losing accuracy.

•   Inter-operability with major EDA backend tools is also a key requirement. For example, it is important to be able to seamlessly back-annotate the extraction model into existing extraction databases created by other tools.

The Helic EM Crosstalk analysis and signoff tools address all the above requirements. Visit the Helic website for further details on how to handle SoC EM crosstalk complexity challenges.

 



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