Standards: Too Many or Not Enough?

There is a huge gap when it comes to a standard format for describing the behavior of memories and reducing dynamic power.


Many of you are familiar with the Betamax versus VHS format wars in the late 1980s. If you’re not old enough to remember that one, you’ll remember HD DVD versus Blu-ray. In each of these cases, there was a clear winner. Semiconductor design has these format wars, too. The problem is that there is rarely a clear winner and worse, sometimes we miss the standard altogether.


There are two industry standard hardware description languages, VHDL and Verilog. Similarly, there are two standards for describing the power intent in designs, namely Si2’s CPF (Common Power Format) and Accellera’s IEEE1801 UPF (Unified Power Format). The complexity of SoC designs has meant an increase in the number of specialist design teams with specific tool knowledge and libraries and IPs written in either VHDL or Verilog and with power intent captured in either CPF or UPF. EDA solutions have traditionally had issues in keeping up with the enhancements to these formats, which has resulted in frustrated designers trying to manually get around tool issues during tapeouts.

Too many standards
Memories constitute a large portion of the chip power in sub-45nm devices. It is also not uncommon to have more than 2,000 memories in the latest networking or mobile applications. Memory power could be as much as 50% of the total power consumed in 28nm technology designs used in the latest mobile devices. These memories come with built-in low power modes, which include clock gating as well as light sleep, deep sleep or shut-down operations to reduce leakage power.

How do you optimize dynamic power in designs with large amounts of memory? You need efficient control logic to meet the performance goals of the design, as well as to minimize total power in different operational modes. Wouldn’t it be nice for the designer to know the exact portions of the RTL code that could be further optimized to minimize dynamic power with available simulation data? Tools exist today that highlight redundant writes or reads from the memories that consume unnecessary dynamic power and the impact they have on downstream registers. However, these tools require a native format to describe the relevant information of the memory behavior, which is typically available in the datasheets.


Vendors have memory compilers that automatically generate models for simulation, synthesis or test. Memories can be modeled in the Liberty format for leakage power and timing or in a behavioral hardware language description for simulation or automatic test pattern generation (ATPG). However, there is no standard format for describing the behavior of memories for identifying redundant reads or writes and the impact of the memory operation on downstream register logic for further clock gating to reduce dynamic power. EDA tool vendors have to work with each memory provider to qualify the corresponding tool constraints with actual behavior of the memory. Wouldn’t it be nice if the Liberty format could be extended to describe the memory behavior for dynamic power reduction, too?

Missing standards
We all know who won the videotape and DVD format wars—it was VHS and Blu-ray, hands down. Unfortunately in semiconductor design, two standards remain for a hardware description language and power intent definition and designers have to learn them both. For memory power reduction, there is no standard and EDA vendors have to invent their own. Hollywood seems to be able to get this right. Why not Silicon valley?

Leave a Reply

(Note: This name will be displayed publicly)