A constraint verification solution plays the role of a devil’s advocate when it brings to the attention of engineers sophisticated design/constraints issues that are not flagged by other tools.
Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no change to the design or constraints. A constraint verification solution plays the role of a devil’s advocate, and is effective when it brings to the attention of engineers sophisticated design/constraints issues that are not flagged by other tools in the implementation/verification flow. A constraint verification solution that inundates an engineer with warnings is, in effect, abdicating the role it was asked to perform and telling the engineer that he needs to manually review his constraints.
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