Pandemics And Panic Chip Buying

By Mark LaPedus - 18 Jun, 2020 - Comments: 0

U.S.-China trade tensions are creating uncertainty in the semiconductor market, but it is also causing another event right now—panic chip buying. At present, some but not all foundry vendors are seeing “rush orders” for select products and are running their fabs at full capacity. It’s not just leading-edge devices, but also mature technologies. A surge of chip orders started in Ma... » read more

Tech Talk: Lower Power Embedded NVM

By Ed Sperling - 12 Nov, 2015 - Comments: 0

Jen-Tai Hsu, Kilopass' vice president of engineering, talks about lower-voltage bit cells, where they fit in IoT designs and how they affect battery life. [youtube vid=dNDkuApHumU] » read more

IP Integration Challenges Increase

By Ed Sperling - 08 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: 55nm

Pandemics And Panic Chip Buying

Tech Talk: Lower Power Embedded NVM

IP Integration Challenges Increase