tag: ARM

AI Accelerators Moving Out From Data Centers
By Ann Mutschler - 15 May, 2025 - Comments: 0

Experts At The Table: The explosion in AI data is driving chipmakers to look beyond a single planar SoC. Semiconductor Engineering sat down to discuss the need for more computing and the expanding role of chiplets with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; ... » read more

Effects Of Hardware Prefetchers For Scientific Application Kernels Running on High-End Processors
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor" was published by researchers at Jülich Supercomputing Centre and KTH Royal Institute of Technology. Abstract "Memory prefetching is a well-known technique for mitigating the negative impact of memory access latencies on memory bandwidth. This problem has become more p... » read more

Report: The Future of AI Processing
By Arm - 14 May, 2025 - Comments: 0

AI is now emerging in everyday use cases thanks to advances in foundational models, powerful chip technology, and abundant data. As a result, new approaches in AI compute are required to deploy these advanced use cases with minimal effort. This report features insights on how to move AI forward from industry leaders at AWS, Meta, Samsung and Arm, and includes research from MIT Technology Rev... » read more

Blog Review: May 14
By Jesse Allen - 14 May, 2025 - Comments: 0

Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

Chip Industry Week in Review
By The SE Staff - 09 May, 2025 - Comments: 0

Check out the Inside Chips podcast for our behind-the-scenes analysis. The U.S. government is rescinding a Biden-era AI export rule that would have imposed complex restrictions on how U.S. chip and AI technology is sold abroad, a move welcomed by companies like Nvidia, reports Bloomberg. While new, simpler guidelines are expected in the coming months, the decision introduces short-term uncer... » read more

Blog Review: May 7
By Jesse Allen - 07 May, 2025 - Comments: 0

Cadence’s Mayank Bhatnagar examines the challenge of ensuring the functional safety of disaggregated designs and how UCIe can serve as a certified way to connect individual components. Siemens’ Charlie Olson explores the causes of inter-domain leakage when a DC path is formed between two power rails and how to overcome the limitations of traditional electrical rule checking. Synopsys�... » read more

Smarter Cars, Higher Stakes
By Sascha Brodsky - 01 May, 2025 - Comments: 0

Artificial intelligence is turbocharging automotive innovation, but it's also unleashing a tangle of high stakes risks that engineers and security experts are scrambling to contain. The push to embed AI deep into today’s vehicles is changing how cars are built, how they handle the road, and how they keep passengers safe. But as onboard intelligence expands, so do the risks. AI systems that... » read more

Blog Review: Apr. 30
By Jesse Allen - 30 Apr, 2025 - Comments: 0

Cadence’s Sree Parvathy points out how electrothermal analysis can help designers understand how temperature changes affect device behavior, such as mobility, threshold voltage, and saturation to mitigate potential failures due to thermal overstress. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the transition towards software-defined products and why companies... » read more

Security Power Requirements Are Growing
By Adam Kovac - 28 Apr, 2025 - Comments: 0

Determining how much power to budget for security in a chip design is a complex calculation. It starts with a risk assessment of the cost of a breach and the number of possible attack vectors, and whether security is active or passive. Different forms of root of trust and cryptography have different power costs. Different systems could require tradeoffs between performance and security, whic... » read more

New Ways To Improve EDA Productivity
By Ann Mutschler - 24 Apr, 2025 - Comments: 0

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling to keep pace with exponential increases in chip complexity in tight time-to-market windows and with constrained engineering talent pipelines. In the past, progress often was as straightforward as improving algorithms or parallelizing computations in a linear flow. But w... » read more

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