tag: BEOL

3D Device With BEOL-Compatible Channel And Physical Design for Efficient Double-Side Routing
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation, and Carnegie Mellon University. Abstract "This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves ... » read more

Improving The Air-Stability and NBTI Reliability of BEOL CNFETs
By Technical Paper Link - 19 Sep, 2024 - Comments: 0

A new technical paper titled "Overcoming Ambient Drift and Negative-Bias Temperature Instability in Foundry Carbon Nanotube Transistors" was published by researchers at MIT, Stanford University, Carnegie Mellon University and Analog Devices. Abstract: "Back-end-of-line (BEOL) logic integration is emerging as a complementary scaling path to supplement front-end-of-line (FEOL) Silicon. Among ... » read more

Building CFETs With Monolithic And Sequential 3D
By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

Impact of Scaling and BEOL Technology Solutions At The 7nm Node On MRAM
By Technical Paper Link - 20 Feb, 2024 - Comments: 0

A technical paper titled “Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories” was published by researchers at Georgia Institute of Technology. Abstract: "While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting the... » read more

Analysis Of BEOL Metal Schemes By Process Modeling
By Daebin Yim - 16 Nov, 2023 - Comments: 0

The semiconductor industry has been diligently searching for alternative metal line materials to replace the conventional copper dual damascene scheme, because as interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. The barrier layer's dimensions cannot be scaled down as quickly as the metal line width (figure 1). Popular barrier materials su... » read more

3D In-Memory Compute Making Progress
By Katherine Derbyshire - 17 Aug, 2023 - Comments: 0

Indium compounds are showing great promise for 3D in-memory compute and RF integration, but more work is needed. Researchers continue to make headway into 3D device integration particularly with indium tin oxide (ITO), which is widely used in display manufacturing. Recent work indicates that different compounds of indium oxide doped with tin, gallium, or zinc combinations may boost transisto... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Etch Processes Push Toward Higher Selectivity, Cost Control
By Laura Peters - 18 May, 2023 - Comments: 0

Plasma etching is perhaps the most essential process in semiconductor manufacturing, and possibly the most complex of all fab operations next to photolithography. Nearly half of all fab steps rely on a plasma, an energetic ionized gas, to do their work. Despite ever-shrinking transistor and memory cells, engineers continue to deliver reliable etch processes. “To sustainably create chips... » read more

New Low-Temp Growth & Fabrication Technology Allowing Integration of 2D Materials Directly Onto A Silicon Circuit (MIT)
By Technical Paper Link - 05 May, 2023 - Comments: 0

A new technical paper titled "Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform" was published by researchers at MIT, Oak Ridge National Laboratory, and Ericsson Research. According to this MIT news article: "Growing 2D materials directly onto a silicon CMOS wafer has posed a major challenge because the process u... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

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